Mendence, the Merger

We have to come up with a clever name for the combination of Cadence and Mentor. Chris Edwards coined* Cadentor, which is actually a pretty decent name. Going the other way, Mendence is too close to "menace" or "mendacity", so I suppose the PR types won't buy that. (When AMD bought ATI, the irreverent press dubbed it DAAMIT.)

Cadence's unfriendly bid to acquire Mentor Graphics is red meat for the EDA blogoshpere! (Be sure to click on that link. It's a fascinating one-page summary of dozens of EDA news & opinion sources.)

I've read many thoughtful commentaries on the possibility. Frankly, most of them are unfavorable on the deal. Some of the substantial analyses:

• Can you guess Gabe's take on Cadence's arrogance?
• Chris Edwards initial take.
• Later, Chris has a very pretty picture of how the companies' main products line up at Overlaps 'r' us.
• Ron Wilson has a possible explanation (conspiracy theory?) for Cadence's motivations.

Two of the more curious quips I read:

• Customers don't want the EDA vendor to provide a complete front to back flow. They want best of breed tools, and for third party companies to link them together. I agree that we need best of breed tools, but not that we need third party companies to hook them together. Are there examples of companies that make a good business of that? That sounds like an ASIC company, and they aren't exactly thriving. There also used to be a company called Reshape that had their own physical design flow on top of commercial tools. But they ended up going out of business.
• Cadence acquiring Mentor could present a big challenge to Synopsys. Well, I don't know. When two established giants come together, what technological advance does that enable? Not much that I can see. A bigger challenge is when a giant acquires a startup with hot new technology: think Cadence with Get2Chip, or potentially Mentor with Sierra Design Automation. One successful big acquisition was Synopsys acquiring Avant! -- I don't know what went on under the covers, but the products were complementary and continued to be successful after the deal was done.

  Of course, there may be "business synergies" -- cutting common administrative and infrastructure costs, and having a bigger menu for "all you can eat" deals. But it's kind of sad if one of the biggest business events in EDA just comes down to that.

*Update: Gabe Moretti lays claim to coining "Cadentor". I'll let Chris and Gabe hash it out.

NEWS FLASH: Cadence Proposes to Acquire Mentor Graphics

And then there were three? This just in: Cadence Proposes to Acquire Mentor Graphics for $16.00 per Share in Cash.

What is Mentor good at? I haven't used their tools recently, but by reputation I think they're strong at

• DFT (FastScan)
• LVS/DRC (Calibre)
• Simulation (former ModelSim)
• Certain pieces of Place & Route (Sierra)

So, does Cadence need some or all of these pieces because they're not strong? That's certainly the case for DFT: Mentor is a leader and Cadence is an also-ran. Or are they just "buying" Mentor's customer base?

UPDATE: Other blog reactions:

• Cool Verification. A verification tools perspective.
• EDA Thoughts. No, honestly -- tell us what you really think of the merger!
• EDA Cafe. Several news releases, including Cadence's own presentation on the deal.
• Sramana Mitra on Strategy. She's been calling for a consolidation in EDA, or some kind of shakeup in the business model. Her post has a good selection of links to her previous writings on the EDA business. This post also has the best comments thread on the topic.

One More Thing: Apple to Tackle Parallel Computing

Apple in Parallel: Turning the PC World Upside Down? - Technology - New York Times Blog quotes Steve Jobs in a discussion of harnessing multi-core computing:

Apple, he asserted, has made a parallel-programming breakthrough.

It is all about the software, he said. Apple purchased a chip company, PA Semi, in April, but the heart of Snow Leopard will be about a parallel-programming technology that the company has code-named Grand Central.

“PA Semi is going to do system-on-chips for iPhones and iPods,” he said.

Grand Central will be at the heart of Snow Leopard, he said, and the shift in technology direction raises lots of fascinating questions, including what will happen to Apple’s partnership with Intel.

Snow Leopard will also tap the computing power inherent in the graphics processors that are now used in tandem with microprocessors in almost all personal and mobile computers. Mr. Jobs described a new processing standard that Apple is proposing called OpenCL (Open Compute LibraryComputing Language) which is intended to refocus graphics processors on standard computing functions.

“Basically it lets you use graphics processors to do computation,” he said. “It’s way beyond what Nvidia or anyone else has, and it’s really simple.”

Since Intel trails both Nvidia and A.M.D.’s ATI graphics processor division, it may mean that future Apple computers will look very different in terms of hardware.

Will OpenCL be an alternative to NVIDIA's Cuda software interface? Read the comments in the NY Times blog for some good technical analysis and the usual passion that surrounds any Apple pronouncement.

Update: see a thoughtful perspective in Chris Edward's blog.

Tantalizing But Flawed

I would love to know the real scoop on the semiconductor challenges and drama involved in developing a high-end gaming console like Microsoft's Xbox 360. A surprising story originating at DAC, EETimes.com - The truth about last year's Xbox 360 recall dangles some tantalizing clues.

I find the story frustrating and a bit flawed in helping to get to the truth of the matter. The article blames Microsoft's troubles on "bypassing an ASIC vendor to go directly to TSMC". But then it mentions ATI Technologies as a likely ASIC vendor. Huh? ATI, an ASIC vendor?

I would call ATI more of a "contract design house" in this deal. They have considerable graphics IP, and designed the GPU for the Xbox 360. (NVIDIA designed the GPU for the original Xbox.) Perhaps Microsoft decided to take only the design (netlist or GDS2) from ATI, and manage the silicon operations and production ramp themselves. That could be where they went astray. By not contracting with an experienced semiconductor company (like ATI or NVIDIA) to manage all the silicon issues, they exposed themselves to more risk. And maybe that came back to bite them in the form of the product defects exemplified by the "red ring of death" and led to product recalls.

Penny wise and pound foolish, Microsoft?

DAC 2008 Meta-Must-See List

That's right, readers. This is a list about lists!

I search the internet, so you don't have to.
-- From "your friend in the EDA Blogging business". (apologies to Tom Shane)

• Cheesy John Cooley's Must See List for DAC
• Ten top technology developments to see at DAC, SCDsource (Richard Goering)
• Gabe's teaser of Gary Smith's list. Looks like you have to visit them at DAC to get the real list. Gary has enough clout that companies issue press releases when they make his list!
• Gary Smith interviewed on YouTube. He names some significant trends in EDA this year, including Analog and Low Power design. The "Software" trend is a little harder to see; I know Gary has been calling for ESL to take off for a few years now.

What "EDA Blogger Birds" Could Squawk About

Next week at the Design Automation Conference, a few leading EDA bloggers are arranging an impromptu "Birds of a Feather" session at DAC. There have been several posts discussing the event. Informal Blogging Event at DAC Gains Interest has a good summary.

Although I'm not sure I'll be going down to Anaheim, I'm very intrigued by the event and would like to attend. What topics would EDA bloggers talk about? Here are some that I would like to discuss with my brethren:

• Online magazines, vendor communities, "DeepChip", and blogs: what each is good for.
• What to write about. What not to write about. What I really want to write about, but am afraid to.
• Frequency and regularity of posting.
• How to build audience. How to track audience. Support each other through linking and commenting. Use pictures? Polls?
• How to foster discussions. Pros and cons of comments. Need for an all-EDA bulletin board.
• Team blogging. (multiple authors contributing to one blog)
• Beyond blogging: social networks (LinkedIn, Plaxo). The Twitter phenomenon.
• Can you make any money? Ads: google or sponsored.
• For readers: how to find and follow blogs.

Incidentally, I've been blogging about EDA and Semiconductors for three years! My first post was about TSMC and low-power design; topics that are if anything, more relevant today.

EDA Earnings Recap

Quarterly financial results are in for the major EDA vendors. This was Magma's turn to disappoint, causing the share price to drop almost 30%. Mentor Graphics stock has performed the best, closely followed by Synopsys. Links to results are below.

• Cadence Languishes On - Sramana Mitra on Strategy
• Magma Design fiscal 1st-qtr outlook disappoints investors.
• Synopsys Posts Financial Results for Second Quarter Fiscal Year 2008. Higher (non-GAAP) earnings.
• Mentor Graphics Reports Fiscal First Quarter Results. Quarterly loss. "Difficult environment". Cost/headcount controls. More importantly, projecting "a strong second half".

Conformal ECO Designer: Successor to ECO Compiler?

Without too much fanfare, Cadence has introduced a tool to help automate ECO creation: Cadence Encounter Conformal ECO Designer Improves Logic Designers' Productivity. At least I didn't see too much fanfare in the engineering press. However, it was mentioned in Cadence's recent earnings conference call:

... Cadence’s Encounter Conformal ECO Designer, a unique and automated capability to address the extreme pressure customers face to deliver on schedule while still achieving targets for product cost and quality. ECO stands for Engineering Change Order and unfortunately for designers these are all too common.

If you've been in the industry a few years, you'll recall that Synopsys had introduced a tool, ECO Compiler, for the same purpose. It never seemed to gain much traction, and Synopsys eventually abandoned it. I never had the chance to use ECO Compiler and I don't know why it didn't succeed. I heard some mention that it's a hard problem to solve, and that the market may have been limited. It's the type of tool that when you need it, you really need it. But you don't need to buy dozens of licenses.

It will be interesting to see how Conformal ECO Designer does -- whether it's better technology, and whether Cadence is able to make the business equation work.

From the Department of Redundancy Department

Dobbs Code Talk - Redundancy in Programming Languages discusses why sometimes redundancy is a good thing. Like in accounting, or computer programming. (Or HDL programming.)

Key conclusion:

Many programming language designers mistakenly assume that removing redundancy makes programmers more productive. ...

Well-designed redundancy can, however, dramatically improve productivity with its ability to uncover errors early in the development process. ...

The trick, of course, is figuring out which redundancies are good, and which aren't.

Countdown to DAC: Design Automation Conference

If you're involved in the EDA or ASIC industries, you should consider going to 45th DAC Home: Design Automation Conference.

There are early registration discounts available for signing up before May 19, so get moving!

I mostly like DAC for the exhibits and the panels. A lot of the papers go over my head -- often PhDs presenting their thesis research on "new routing algorithms that did x% better on university benchmarks."

Profile-Guided Optimizations for Software Development

Not being a commercial software developer, I hadn't heard of Profile-Guided Optimizations (from the blog of the Opera Browser Desktop Team), but it sounds clever: run some "real-world benchmarks" through your application, and then recompile the application to optimize for the code path followed most often.

Is this common in software engineering? Do EDA tools do tricks like this for best performance? Let's hope so.

Weirdest EDA Acquisition Ever?

Just read about Synopsys Invests In Prover Technology and I decided to post it without further research, just to react to the article.

From reading the press release, I'm really left scratching my head. Is this for real? It's not April 1, right? I am very curious to see how much synergy exists between "railway signal design automation" and EDA!

A missing link in tech history

For those interested in the history of our industry -- and who of us shouldn't be? -- here's a news item of the pre-electronic (even pre-electrical) origins of computing:

A missing link in tech history - San Jose Mercury News tells the story of the construction of the "Babbage Difference Engine", which was designed but never built by 19th century inventor Charles Babbage. This is truly an engineering marvel. Frankly, I'm amazed that it works! Here's a video showing some details of this mechanical masterpiece in operation. I certainly want to head over to Computer History Museum in Mountain View to check it out.

While we're on the subject of history, here are other good resources to check out:

• Intel Museum (online and in Santa Clara)
• The Chip History Center (online)
• IEEE Virtual Museum (online)

Blessed Perl

I just spent three days in great Advanced Perl Programming class taught by the Anderson Software Group. This was the best class I've taken in a long time. One of the most satisfying things to do at work is to develop a well-crafted program (usually in Perl) and see it working smoothly to automate my own or someone else's work. The class exposed me to things I'd always wanted to know about Perl, including Object-Oriented Perl, GUI building, and interfacing to databases, networks and C programs. Great stuff!

We worked from Anderson's class notes, but the reference text for the course is Advanced Perl Programming from O'Reilly. See my other favorite programming books on the CAD Engineer's Bookshelf.

I'm hearing rumblings that Python is a "better Perl", designed from scratch for object-oriented programming. I guess it lacks that Perl syntax that can make a program look like hieroglyphics? This sounds like the next language to learn.

Apple buys a CPU company

Wow, I didn't see this coming: Apple disses Intel's Atom, buys PowerPC designer P.A. Semi. Very interesting. I had been vaguely aware of P.A. Semi, but didn't know where they'd find big demand for their advanced PowerPC CPU. And Apple has become more of a system designer than a chip designer. So I wouldn't have guessed that they'd buy a Semiconductor IP company. Some have twittered, "why not AMD?" For that matter, why not Transmeta, if they're looking for a very low power mobile CPU?

Congratulations, P.A. Semi! It will be fun to see how this plays out.

Forbes article

Update: color analysis from Chris Edwards.

Stop Me Before I Schwag Again

Just got back from the TSMC Technology Symposium. I'll think about what I can share from that always-valuable event. But what I have on my mind, in the wake of Earth Day, is the schwag that us engineers accumulate, and how we just can't stop it!

• Another conference, another tote bag. My closet is overflowing! And, another non-recyclable badge lanyard that will have to be thrown out. I wish that conference organizers would "think green" and give out less "junk", and distribute reusable or recyclable merchandise. Of course, I need to look in the mirror as well. Why can't I say "No" to this stuff? I'm making some progress in turning down trinkets, but it requires eternal vigilance.
• Will engineers do anything for a T-shirt? Although I love them, my home is overflowing with shirts from vendors and from runs and rides that I go on. I've become more discriminating: a vendor's white t-shirt won't make the grade, nor will colored ones with a non-clever design. What I am amazed by is how easily I can give these shirts away to other engineers. I put a vendor's black t-shirt out in the break room with a "Free Shirt!" Post-It note. Within five minutes, it disappeared! I have successfully followed the mantra Reduce, Reuse, Recycle. In the words of Fake Steve Jobs, namaste.

DFM heads into the foundry

And we're back to the "Hacking Cough" blog for this analysis of DFM heads into the foundry. The post explains an innovative announcement from TSMC whereby they will offer as a service Blaze DFM's power & variation optimization capability. The innovative part is that instead of a chip design company buying the EDA tool, you pay for it as a service from your foundry (exclusively TSMC at this time).

One thing I'd wonder about is how design teams can accurately convey their timing environment to TSMC (across all modes and corners) such that these optimizations don't break timing. Running sign-off STA is not quite as simple as "just send an SDC file over". :-)

Good Blog, Odd Name: Hacking Cough

I've found a semiconductor blog to recommend, with the curious name of Hacking Cough. It's better than the name implies! One more salvo in the 32nm war is a nice overview of where IBM, Intel, TSMC, and others are headed with their 32nm process technology recipes, and their different approaches to solving scaling and power consumption problems.

NVIDIA Powers Hardware-Accelerated SPICE Simulator

The multi-core future of EDA is just starting to appear. NVIDIA Powers Hardware-Accelerated SPICE Simulator is an exciting announcement of a real EDA application (Fast SPICE) running on massively parallel GPU hardware. Will general purpose GPU (GPGPU) computing become the acceleration platform for EDA?

SNUG SJ 2008 Report

For my report on this year's SNUG San Jose conference, I'll point out the major themes that cropped up across multiple sessions. If you're a Synopsys customer, you can see all the papers and presentations at the SNUG web site.

Low Power Everywhere

Low Power support is becoming pervasive in design flows. Both in design and verification, tools are supporting techniques such as Clock Gating, Multi-Vt, Power Gating, State Retention, Multi-Voltage, and Dynamic Frequency and Voltage Scaling.

Of course, for an EDA company, this requires a new name to designate these new features. So, Synopsys is calling it their "Eclypse" flow. (Note the funky spelling to give fits to spell checkers everywhere.) I don't think this name matters much to ASIC engineers -- do you care what the "Galaxy" or "Discovery" platforms consist of?

DC Topographical Uber Alles

DC Topographical, which is Design Compiler's inclusion of "virtual layout" during synthesis, is becoming mainstream. The newest edition is DC-Graphical. It adds congestion reporting and optimization, and a GUI to help visualize and debug virtual layout-related issues. It certainly makes more sense than using traditional wireload models, though you could run into correlation issues if the virtual layout floorplan is very different from actual.

Blues Compiler Rocks

The biggest treat of SNUG was the first public west coast performance of Blues Compiler, Synopsys' house band. To be honest, I hung around to hear them play out of curiosity. I figured it would be a bunch of guys who used to play in college and still liked to goof around with their instruments. Boy, was I in for a pleasant surprise! Featuring CEO Aart on electric guitar, and "Diva" Joanne W on vocals, this band absolutely rocked! They sounded very professional and played a number of sweet electric blues/rock songs. I'd compare their sound to Janis Joplin's, who I am a big fan of. Absolutely recommended to check out if you get a chance. They usually play at Boston SNUG, and I hope they'll be back in San Jose in the future.

A review of the performance would not be complete without a nod to the "Solid Gold" Marcom Dancers, who succeeded in getting a bunch of engineers in a banquet room dancing to the tunes. Quite an accomplishment. I was impressed and hope to get dancing lessons from "Crazy Legs" Shankar H in the future.

Synopsys to Acquire Synplicity

I had missed the news of Synopsys to Acquire Synplicity, Inc. until Aart de Geus mentioned it in his SNUG keynote speech.

Sounds like Synopsys is pretty interested in Synplicity for the "rapid prototyping" capability to check out ASICs before taping them out. The price wasn't too high, either.

I sat with a couple of FPGA designers at SNUG lunch and they spoke highly of Synplicity's FPGA synthesis -- definitely superior to what one can get through the FPGA vendor. With better quality of results from Synplicity, designers may fit their design into a smaller FPGA part, which saves big bucks in production.

Low Power Sessions at SNUG 2008

I was at SNUG, the Synopsys Users' Group, for the past three days. It was an excellent and very practical conference, as always. I will post more of a trip report soon, but one of the big themes was Low Power Design and Verification. Synopsys' low-power point man and blogger, Godwin Maben, even gave a general session (keynote) speech on it.

Godwin has kindly compiled and linked to the list of low-power papers at this year's SNUG, which you can see in his blog post Magic Blue Smoke � Blog Archive � Low Power Sessions at SNUG 2008. Note that you must be a Synopsys customer (SolvNet login) to see the papers.

The Future is Multi-Threaded

Richard Goering's article Synopsys pledges multicore support for EDA applications covers the current state and future claims for multi-threaded EDA products. Synopsys has made a big announcement about a multicore initiative, and Richard also notes the vendors (mostly startups) who are already offering such products.

I hope that Synopsys isn't just blowing smoke and will deliver multi-threaded applications in 2008. I'm no software engineer, but I thought it would be pretty difficult to retrofit multi-threading in these gargantuan EDA products, some of which have been around for many years.

We really need multi-threaded applications. Most servers have multiple CPUs with multiple cores each, yet are limited by memory as to how many EDA processes can run at a time. Often, you can only run one job because you need all the memory on the server to synthesize or place & route that design. Multi-threading should deliver greatly accelerated performance as those other idle cores contribute to the job at hand.

Some of the terminology gets confusing. In this article, "multi-threaded" and "multicore" are seemingly interchangeable. And then there is "distributed processing". I think of multicore as describing the hardware (CPU), and multi-threaded as describing the software architecture that includes shared memory access. And "distributed" means running on different physical servers, with separate memory models. Do I got that right?

SNUG San Jose is Coming

The 2008 edition of SNUG (Synopsys Users Group) San Jose is coming March 31 - April 2, and registration is now open.

This is one of the most useful conferences if you use any Synopsys tools. The papers are very practical, and you can meet engineers who are doing real hands-on ASIC design. The Synopsys tutorial and product updates are very professionally done, and presented by their "star" CAEs who really know the products. The panels can be good, though they're usually not as spicy as the inter-company debates at DAC or the dog fights that John Cooley sets up.

Hope to see you there!

Aart de Geus Profiled in IEEE "The Institute"

The IEEE's monthly newspaper, The Institute, features Synopsys CEO Aart de Geus for its monthly "member profile". The article recognizes both his business accomplishments in founding Synopsys, and his significant community support, especially in the area of education. See Aart de Geus: At the Heart of High-Tech.

It's an Analog World, After All

Until new markets like DFM and ESL take off, the big EDA vendors are going after Cadence's Virtuoso franchise for Analog/Mixed Signal design. This has been a safe haven and cash cow for Cadence.

While I've caught mentions of Synopsys working on an analog design product, Magma has been the most forthcoming so far. Last week at MUSIC (Magma Users' Group meeting in San Jose), they announced

• Titan, an Analog design entry system. See Magma Introduces Titan -- First Platform to Combine Full-Chip, Mixed-Signal, Analysis and Verification for IC Design and a video interview Cooley does Rajeev on his new Titan.
• Acquisition of Sabio, an Analog "process migration" tool. See the press release Magma Acquires Sabio Labs, Enhances Titan Mixed-Signal Design Platform.

Titan  is at first glance a "me too" product, though attractive if it offers better integration, performance, and pricing. Sabio has a lot of grand claims from Magma -- if they deliver, this technology could be very valuable to customers.

HD-DVD is Dead. How about Dueling EDA Standards?

As anyone following consumer electronics knows, the nascent high-definitition DVD market was held back by dueling standards: HD-DVD, backed by Toshiba/Microsoft, and BlueRay, backed by Sony and many movie studies. Microsoft XBox 360 had an HD-DVD option, and Sony PlayStation 3 had built-in BlueRay capability.

This unfortunate situation harkens back to the old "Beta vs. VHS" VCR format fiasco. Sony lost that battle, but in the case of BlueRay, they've come out on top. Nearly all studios and retailers have announced support for BlueRay instead of HD-DVD, and it looks like the industry will finally be able to focus on who can produce the best products at the best prices.

What does this have to do with EDA? Unfortunately, our industry is also plagued by dueling standards, and by companies jealously protecting de facto standards. In the beginning, there was Verilog, which Cadence refused to open up, spawning many man-years of duplicated work in VHDL. It happened again with Synopsys' .lib format. When Synopsys refused to open that up that standard, the industry spent a bunch of time on a competing OLA/ALF standard. Finally, Synopsys opened up "Liberty" and we can focus on who has the best tools, with library access for all.

In the present day, we still haven't learned! I hope for a quick and orderly consolidation of

• Advanced timing modeling: CCS (Synopsys) vs. ECSM (Cadence)
• Low Power Constraints: UPF (Synopsys) vs. CPF (Cadence)
• Though I'm not a Verification guy, it sounds like the same thing is happening with VMM (Synopsys) vs. OVM (Cadence/Mentor)

Come on, big vendors! For the sake of the your customers and to have a dynamic, innovative industry, tear down those walls!

Synopsys Doesn't See a Slowdown, Either

Similar to Magma's earnings report for this quarter, Synopsys doesn't report seeing a slowdown in their business. This has been much on analysts' minds, and the subject of pointed questions in conference calls since Cadence's disappointing report. Aart de Geus, Synopsys CEO, said "we project that EDA will grow and we will gain market share in 2008, all under our very stable business model." For more, see the earnings announcement and conference call transcript below.

• Synopsys 1st-qtr profit nearly doubles; shares up
• Synopsys F1Q08 Earnings Call Transcript

That's Innovation!

EDN's 18th Annual Innovation Awards Finalists - EDN lists the nominees for the 18th Annual EDN Innovation Awards. It's a quick way to see "what's hot" in a diverse number of fields, which happens to include EDA (in two categories).

What do you think about the finalists? Are the most innovative products that you would pick on the list?

What is PDF's Solution?

I don't want this blog to become "watching the EDA train wreck", but what is happening to the industry recently? Sramana Mitra's blog alerted me to PDF Solutions in her post PDF Offers Value, Finds Scaling Difficult - Sramana Mitra on Strategy.

The stock has dropped to an all-time low:

Sramana is suggesting that PDF has real value add and that the company should be an attractive acquisition candidate to a major EDA vendor. I do agree, DFY/DFM products that really work have a tangible benefit on chip companies' bottom lines. It's easier to appreciate and quantify DFM than that other great hope of EDA, "ESL".

One drawback is if the customer base is just foundries (like TSMC) and IP providers (like ARM Holdings), then the number of customers is not very large. Many fabless semiconductor companies won't need a big investement in DFM, at least not until such tools move up into the design implementation process.

Profile of ATopTech, P&R Upstart

ATopTech is an EDA startup with a goofy name but a hot P&R product, according to rumors on John Cooley's DeepChip site. Does the Industry Need Another P&R System? is an interview with Eric Thune, the VP of Sales & Marketing at ATopTech. He describes a lot of technical features of the tool, and makes specific claims of where they are better than the competition.

The technology just sounds mind-boggling. I'm sure there are other EDA systems with such impressive algorithms, but to see all the capabilities enumerated and to try to imagine how to do it all -- why it makes my head spin as "just another Perl hacker". A couple of quotes that impressed me: "If you look at many of the members of our team, you see that this is their third commercial place and route system that they have built. They know all about the challenges and the mistakes that have been made." and "The feedback from our customers is that our R&D has done a phenomenal job on customer request. They turn those around quickly. With some of the big guys, they do not see a release for six months. Our customers are asking for things and seeing them in days or weeks."

Normally I don't like the extra-long interviews posted on EDA Cafe, but this interview is worthwhile if you're interested in "what's hot" in IC implementation.

Sramana Crunches EDA

I blogged an alert about Cadence's troubled guidance in CDNS, Like a Rock, and now, respected business blogger and journalist Sramana Mitra has weighed in with an in-depth analysis at Cadence Crashes. Now What?.

As I've commented to her before, I like her "big picture" financial perspective on the EDA industry, but as an engineer, I feel she gives too little weight to the strength of each company's technology. She argues that the big guys will win in the long run because of their ability to deal.

EDA Slowdown? What Slowdown?

Coming one week after Cadence announced a weak outlook and the stock cratered, we have Rajeev Madhavan, Magma founder and CEO, telling investors

[Regarding] the economy and its impact on our industry and our customers: We do not believe the economy is having a significant impact on our business. Our customers continue to invest in Magma tools because they provide the most productivity. Magma grows by taking market share and does not rely on overall EDA industry growth. We continue to provide new products that expand our total available market and as long as these products increase customer productivity, Magma will continue to take market share.

-- Magma F3Q08 (Qtr End 12/31/07) Earnings Call Transcript - Seeking Alpha

Ouch, talk about kicking your competitors when they're down! As you can see by this chart, LAVA has outperformed its major competitors and the general market over the last year, though in today's market, that means they've only produced a 3.6% gain.

Prestigious Turing Award presented for Model Checking

Dr. Dobb's Journal: 2007 Turing Award Winners Announced gives details on the recipient of the annual Turing Award, one of the most prestigious awards in Computer Science. It's nice to see an EDA field being so recognized-- I've always admired the complexity of EDA problems and the intellectual power harnessed to solve them.

My impression is that Model Checking is still a nascent field of EDA, yet these guys invented it way back in the early 1980s! Talk about a long gestation period.

Has their work directly gone into any current-day EDA tools? Is there a rightful heir to this seminal innovation?

ULTRA Low-Voltage Design Reported

Energy-efficient Microchip Could Result In Cell Phones Staying Charged 10 Times As Long, Self-charging Electronics describes a design done by MIT and TI researchers showing operation at 0.3 volts. It includes several interesting features, such as

• On-chip DC converter to reduce voltage
• Designed to minimize manufacturing variation
• 0.3 volt operation at Idle mode, which implies Dynamic Voltage Scaling (DVS).
• Memory uses an eight-transistor bit cell, which improves retention at low voltage.

Lowering voltage is actually the standard for lowering system power," said Dean McCarron [President of Mercury Research]. "The challenge is that when voltage gets to a certain level, generally around 0.8 to 0.9 volts, making the chip work becomes more difficult. You know, 0.9 was thought to be the floor, and these guys have broken through the floor.

The researchers are describing their work in a paper presented at the International Solid State Circuits Conference in San Francisco. See also this Computerworld article.

CDNS, Like a Rock

The Market has really hammered some tech stocks (SPWR and VMW come to mind) this year, and today is Cadence's turn. Shares are down 32% today, after last evening's earnings announcement.

It's the "usual" story of decent historical financial results (Earnings meeting expectations, Sales a bit short), but the dreaded "weak guidance" for the future.

I'll be looking for the conference call transcript to see if the poor outlook is blamed on a weak overall economy or semiconductor industry, or if it seems to be particular to Cadence or certain product lines.

Update: Management's Earnings Conference Call Remarks are here. There's no specific information about company or product weakness. Rather, it says

As a result of our discussions with customers in Q4, and our assessment of an increasingly aggressive pricing environment that we have not seen during the past few years, we believe it is prudent to plan our 2008 business conservatively.
...
The current environment is more uncertain and the value discussions are longer and are harder than in the past several years. However, our strategy is intact, our technology has never been stronger, and we are dedicated to preserve the value of the solutions we are providing to customers.

Sounds like it's those darn stingy customers causing the problem. :-)

All-time Most Influential Technologists

Intel ... assembled a panel of experts including academics, journalists and independent third parties to vote on technology's 45 most influential people: HEXUS.net - Headline :: Intel lists its 45 most influential technologists : Page - 1/1

This is really an esteemed list. Tim Berners-Lee deserves a Nobel prize for the impact that the Web has had, and will have, on the world. I wouldn't put the founders of Google so high, though. Isn't Google just the search engine du jour? If this list was made a few years ago, would the founders of Yahoo or even (shudder) Netscape or AOL have been listed?

Who else doesn't belong? Who else is missing?

Check out the comments below the article for Wikipedia links to biographies.

Best Technology Business Blogs

Recommended Blogroll: Good Technology Business Blogs - Sramana Mitra on Strategy

This is Sramana's list of favorite blogs in this field with her descriptions. Worth a look, especially given that she is a published Forbes magazine author!

2008 Technology Winners and Losers

No, I am not talking about tech stocks! Please, let's not talk stocks so far in 2008. :-(

Instead, I refer you to IEEE Spectrum magazine's list of "winning" and "losing" technologies.

For chip geeks, a particularly good one is The Ultimate Dielectric Is...Nothing, highlighting IBM's research to create a vaccuum between chip interconnect. Not only is the technology very cool, but I'm really impressed by the writing in this article. The author is able to explain things like photolithography and crosstalk in layman's terms. Take a look; it's a nice piece of work.

I am so impressed by the cutting edge semiconductor R&D done at IBM and Intel. They are constantly pushing the envelope and competing very ably with giant foundries like TSMC. It's surprising that these tech heavyweights don't do more COT (foundry) business. I wonder if it's a lack of ability to set up the business and customer service, or a lack of desire, i.e., that they have more profitable things to do with their fabs.

An Industry Giant Departs

The Consumer Electronics Show (CES) is happening this week, with lots of big announcements for all us tech developers and consumers.

On the personal side, this is the last CES where Bill Gates, Microsoft founder and CEO, gave the Keynote address. Here's a video about his last working day at Microsoft.
Bill Gates Last Day CES Clip

Semiconductor Co. Gets R-E-S-P-E-C-T

Shoot To Kill - Forbes.com is the cover story on Forbes magaznie's Company of the Year. The honor goes to the graphics chip leader NVIDIA (aka Graphzilla).

The article itself is good. It does a nice job of explaining GPUs and CPUs in laymen's terms. There were only a couple spots where I thought "what on earth are they talking about?" And, their highlights of the company's history and CEO are well done.

Check it out. It's nice to see one of our companies lauded in the mainstream media!

Financial Perspective on EDA Companies

Update: Added Magma link.

Ms. Sramana Mitra has posted a series of articles with her commentary on how EDA vendors look financially. Take a look at her posts on

• Cadence
• Magma
• Mentor Graphics
• Synopsys

May you all have a restful year in and wishing all peace and prosperity in 2008.

John

EDN Hot 100 Products of 2007: EDA

Whoever said EDA is boring? From a technical innovation standpoint, it is pretty exciting. From a financial standpoint, not so much. :-)

EDN Hot 100 Products of 2007: EDA - 12/14/2007 - EDN: "EDN's editors offer up their annual list of the year's 100 most significant ICs, components, buses, boards, EDA tools, power devices, test instruments, and more."

I've worked with a couple of these, and plan to learn more about the others.

Happy Birthday Mr. Transistor

It has aged very well, and is helping pay a lot of our paychecks. We truly stand on the shoulders of the giants who invented and advanced such a seemingly simple yet amazingly versatile and powerful device: The transistor turns 60 | Between the Lines | ZDNet.com

Along the same lines, Fairchild, the first big semiconductor company and training ground for countless startup founders, recently celebrated its 50th birthday.

I've often thought that if you really, really grokked the transistor, you'd be all set to contribute to large swaths of electrical engineering. I'm certainly not as facile with all its behaviors as I'd like. How long would it take to really understand, thoroughly and intuitively? A year? Four years? A career?

What a Motley Crew

I just had to share The Programmer Dress Code for the fine pictures therein. These guys are the giants of Computer Science! I recognize most all the names, though not many faces. I guess they're not too photogenic. :-) I recognized Knuth, Stallman, and Wozniak.

What I especially love is that as I write this, I am sporting a beard and am wearing a red plaid flannel shirt! If I just would let my hair go wild, perhaps my scripting will improve.

Cadence Cutting

Sounds like some cutbacks are happening at Cadence. There's this post on the Yahoo! message board, and also rumors of cancellation of a "high-profile" project. I don't follow the stock closely, but it dropped over 20% in the past six weeks, much worse than its EDA peers. The stock price drop coincides with their last quarterly earnings report. These are always hard for me as an engineer to decipher. It says nothing about Cadence's technology, and is all about a "new licensing model". I just know that if I had a nickel for every time an EDA vendor changed their licensing model, my kid might be getting a PlayStation 3 for Christmas. ;-)

Anyone know details of what's happening at Cadence? I wonder how other EDA vendors faring with projects and hiring?

Bubble 2.0 Video

This funny well-done Bubble 2.0 video has just surfaced: Too bad all the hype is about Web 2.0 instead of EDA and Semiconductors. :-( Hey, at least we produce something tangible.

This video itself is inspired by this excellent video of Billy Joel's song.

China Envy

"Everyone knows" that China may be the economic powerhouse of the 21st century. This columnist, writing China: A Tech Powerhouse? - Columns by PC Magazine, sums up the case in the most ebullient terms. So, maybe it's time to start that long intended plan to learn Mandarin?

But this may not be the best moment to invest financially in China, as their stock market looks like a bubble waiting to pop: China: First BRIC To Crumble?

Aart de Geus, Renaissance Man

Congratulations are in order for Aart de Geus, Synopsys' CEO. Last week, the Silicon Valley Leadership Group honored him with its Spirit of Silicon Valley Lifetime Achievement Award. Read all about it in San Jose Mercury News - Takahashi: Synopsys leader's quiet impact.

I had the pleasure of attending the awards banquet, since my company purchased a table.

The keynote speaker for the luncheon was California Governor Arnold Schwarzenegger. It's the first time I've seen and heard "Ahnold" live, and he is quite impressive. He is very charismatic and his answers to audience questions made a great deal of sense. Of course, sound bites are easy and the devil is in the details when enacting policies and making hard choices. Voters are not easy to please. (We'll have our cake and eat it too, please.)

But enough of the Governator. For Aart, there was a fine tribute video shown with testimonials from business and community leaders. Aart was gracious and humble in his acceptance, noting all the contributions from his family, the Synopsys Foundation, and his colleagues in the Leadership Group.

Aart has been a true leader in the local community and Synopsys has been especially strong supporting Education and Science Fairs. Congratulations on a well deserved honor!

You Know You're an Engineer When...

I'm sure you've seen such engineering humor before, but this list has some clever points and is written by a software engineer at Google: Niniane's Blog: You Know You're an Engineer When...

Check out the rest of Niniane's Blog, too. She writes with great openness and gives insight into life at Silicon Valley->Web 2.0->Google.

Penryn Arrives: Intel at 45 nm

Is this the first production 45 nm chip? Penryn Arrives: Core 2 Extreme QX9650 Review It kind of snuck up on me. Intel is firing on all cylinders for the last year or two. Nice architecture, and a full process node ahead of AMD.

The secret sauce in their 45 nm recipe is "HK+MG", for High-K dielectric and Metal Gate. Cool stuff, this High-K addresses the huge problem of gate leakage as the process scales down. The power reduction claims are very impressive.

One nit that's always bothered me is that we all design in CMOS, and the "M" in CMOS stands for Metal. But the gate hasn't been metal in ages! Now it is metal again and it's a novelty. What is old is now new again.

Also, take a look at the die shot. That's two duplicate cores and a huge cache. Hey come on Intel, design some real gates, like the Graphics companies do! :-)

Friday Fun with "Steve Jobs"

One of the funniest blogs going right now is The Secret Diary of Steve Jobs. Lots of unfiltered opinions about the Electronics and Entertainment (media) industries. It's a parody, but some of the posts are scathingly spot-on.

Oh, and it's rated PG-13 for language. Don't say I didn't warn you.

Maybe Sun is onto something

Jonathan Schwartz could have been paraphrasing me when mentioning those unimpressed by Sun's latest CPU announcements.

Those who love desktop computers thought we were daft. Here we had what looked like a slow chip, optimized for something no home user really cared about (lowering power bills, running multiple OS's and minimizing space). And to make matters worse, we removed support for floating point precision math on the chip - to save more power and space. Desktop users (who play games that often feast on floating point processes) thought we were loons, but most datacenters didn't notice (very few datacenters use floating point).

But his blog posting Jonathan Schwartz's Weblog: Hugging Customers (Not Trees) shows that there's a method in Sun's madness. Might Sun be able to compete with Intel after all? Let's hope so, as competition is good for the industry, and AMD has been struggling against Intel recently.

nSide NVIDIA

If you love chip design and/or are curious to look into one of the most successful semiconductor companies, you'll enjoy looking at nSide NVIDIA.

The Failure Analysis equipment is super-high tech. I learned a few things about how chips are made to tell their secrets. Also see the campus, compute farm, cafeteria, and even the beloved high-tech coffee machine!

Even Gerald Hsu has a blog

Even EDA ex-Avanti CEO Gerald Hsu has a blog brings back the memory of perhaps the most colorful and crooked character in EDA history.

I couldn't find his blog. The link is to an audio interview puff piece. I've always wanted someone to write the whole story of Avant!'s theft of source code from Cadence: how they did it, and most incredibly, what were they thinking? It would be a business thriller, no doubt.

It's sad that one conspirator (an EE PhD) ended up going to prison at San Quentin while the CEO walked free and is doing business in Asia.

Looking for Good Training

I wanted to poll blog readers for their experiences and recommendations on technical training. Specifically, I'm looking for a System Verilog for Design class. Have you taken one of these and what did you think? In general, what has been your experience with HDL or EDA training?

For the class I'm looking for, I found these providers

• Doulos (a new name to me)
• Sunburst Design (Cliff Cummings)
• Sutherland HDL (Stuart Sutherland)

AMD Salvages Phenom

My first reaction to AMD announcing a three-core processor was that it sounded weird. Why design a three-core CPU? And one of the explanations I heard was even more contrived, something like "you could be running a demanding video application using two cores and have another core running virus scan". Ah yes, the price we pay for security.

But upon a little more reflection, I have to agree with Larry Dignan of ZDNet that AMD’s triple core chip is a nice intersection where engineering meets business savvy.

Of course! It's not a three chip design. It's the four-core Phenom chip with one defective core disabled. AMD gets to salvage a "non-prime" part, and the consumer should get a good deal on a CPU that's better than dual-core.

This is a nice side benefit of highly-parallel designs, as long as they're designed to degrade gracefully.

A Vast EDA Conspiracy

several folks noted that one of the saving graces—one of the things that will seemingly prevent EDA from getting hit too hard by Piracy--is that EDA software tends to be extremely buggy

-- Websites offering a Synopsys tool for $20? EDA pirates or legit? - Between The Lines - Blog on EDN

I've been banging my head against the wall the past few days trying to debug EDA software that the AE hasn't been able to figure out, and now this! Do EDA vendors intentionally let software quality wane to ensure maintenance revenues and prevent piracy? I always love a good conspiracy theory ...

EE Times Emerging Startups

EETimes.com - EE Times updates list of emerging startups proves that the innovation and money is still flowing in our industry.

Trends

• Fabless Wireless
• Asynch logic IP
• Multi-core programming

Companies

With respect to EDA, here's what caught my eye:

• Athena Design Systems Inc. www.athenads.com
• Blaze DFM Inc. www.blaze-dfm.com
• Calypto Design Systems Inc. www.calypto.com
• Dafca Inc. www.dafca.com
• Imperas Inc. www.imperas.com

We will use no software before its time

Reading about the reluctance of IT departments to move to Vista in the articles Still missing from Vista SP1 fix list: a really good reason to leave XP : Good Morning Silicon Valley and here makes me think of how we treat major new releases of EDA tools. Would you bet your chip on a new tool release named like "7.0"? I sure wouldn't. You gotta wait until -SP1 or later. What's that called? Letting the other guy find the bugs?

Mamas, Don't Let Your Babies Grow up to Be ...

... Engineers?

Former EE Times editor Brian Fuller recaps a spontaneous debate between semiconductor panelists regarding what field your children are studying.

It's a touchy subject among engineers. Most of us still love engineering. But, we may have seen career frustrations, especially in the aftershocks of the .com bubble bursting. In America, there's the sense that some small percentage of engineers do fantastically well if they join the right start-up, but most enjoy an above-average though not large lifestyle. It seems like the folks doing really well and making it look easy are the lawyers and MBAs.

Brian presents the two points of view in Greeley's Ghost: Panel dispatches. Peggy the EDA analyst has kids studing hard sciences -- good for her. Jack Harding, former Cadence CEO, has kids studying Liberal Arts. Fair enough (as long as it's a "respectable" Liberal Art ;-). But what I found interesting was his justification:

It's where you sit in the value chain that makes the difference." IBM, he argues, doesn't make money on its technology development. It makes money taking other people's technology and finding ways to make profit on it. It's hiring not engineers but liberal arts and business people. In housing, he added, the contractor takes the risk and gets the margin. The plumbers, framers and electricians he hires (you can't build the house without 'em!) get an hourly wage.

Grudgingly, I'd have to admit there's truth to this. But it's really more of a justification of the value of an executive over an individual contributor. And who says that executives can't be engineers?

Is EE Times Outsourcing Journalism?

From reading earlier posts in this blog, you know that I regularly read EE Times. It's my main publication covering the business and technology of Electronics, Semiconductors, and EDA. I find it more relevant than my IEEE publications!

But, lately I've become concerned about cutbacks.

• First they downsized the size of the papers (physically), and eliminated that funky old favorite "Immortal Works".
• Next, they made substantial staff cutbacks, including axing Richard Goering and their Editor in Chief.

Maybe this is the inevitable consequence, but lately I've noticed that many of their features are written by industry sources rather than full-time journalists. In moderation, this isn't a bad thing. Practicing engineers can give a valuable real-world perspective on problems we're seeing and how to solve them. But in excess, I'm worried that EE Times will become a collection of "advertorials". Indeed, some of the articles I read from "industry voices" proceed to describe some very specific, not widely recognized problem, and then lay out a solution: which, coincidentally, happens to be exactly the problem the author's company addresses! This can be self-serving and less than objective.

Let's hope that industry publications will strike a healthy balance between problems encountered by in-the-trenches engineers and objective analysis of the major issues and trends. There is significant value in traditional journalism. What else are you gonna do, get all your news and opinions from blogs??? :-)

Intel Uber Alles?

Intel and the Power of Having a Monopoly - Seeking Alpha is an analysis of Intel's long-term business prospects from an investment advisor's perspective. The author concludes that Intel has a very bright future.

Reading it, it makes it sound as though AMD might was well raise the white flag right now. Intel is the Borg.

I think this analysis is mostly right, but AMD has surprised us once in the past. It will be interesting to watch if they can come back to fight another day.

Cooley Does Gary Smith?

Cooley Does Gary Smith is a webcast with a cheesy title but a nice discussion of emerging EDA tools from DAC this year. It's worth a watch to get ideas for companies to keep an eye on.

I like Gary Smith's perspective, even though I don't agree with all of his picks. His picks I'm not familiar with are interesting, and for the tools that I use or am interested in, I know that his take is pretty good.

Great article on Statistical STA

EETimes.com - Practical Applications of Statistical Static Timing Analysis is a great article on statistical timing analysis! Quite in-depth and comprehensive for a two-page article.

Interesting that the authors are from Cadence. I didn't know they were big players in the STA arena. I know they have an "Encounter" timing system, but I'm not familiar with how advanced or accepted it is.

The article reinforces my view that statistical STA is "not ready for PrimeTime". That pun is not a slam against Synopsys! I mean that there needs to be a lot more support from the foundries and understanding by the design community before there's much adoption of SSTA for production chip timing.

Another good article, which was just published and is written by Extreme DA's founder, is Statistical static timing analysis: A view from the future.

The EDA Dozen (Startups to Watch)

We need more excitement in the EDA industry after the layoffs of analysts and journalists following the field. Here's a start. The EDA Dozen lists that the top start-ups as anointed by EE Times.

For some of these, I'm very familiar and interested in what they're doing. For others, I can hardly understand how their technology works and how likely it is to catch on. I'll let you determine the What's Hot and What's Not for yourselves, but this list can get it started.

Fare Ye Well, Richard Goering

I had to do a double-take when I read Gabe Moretti's column The Week after DAC: some lingering thoughts | EDA DesignLine. Buried therein was the comment about "where the industry is going, a clear indication came this week with the layoff of Richard Goering, the deacon of the EDA journalists core". At first I skimmed over this, thinking that he was talking about Gary Smith, whose departure from Dataquest has been previously lamented. But no, Richard Goering, the main EDA journalist at EE Times forever, has been laid off!

This is a sad development, both for what it may say about the EDA and Journalism industries (I love both), and personally for Mr. Goering, whose writing I have long admired. Let's hope he lands on his feet and happily applies his skills elsewhere.

Other mentions of the news:

• Richard Goering gone from EETimes?
• Another Grim Day for EDA: Richard Goering laid off from EE Times--CMP layoffs

Q: Whither EDA? A: Private Equity?

Welcome to DAC week! I'm not there, but I expect to see a flurry of announcements and will be looking to keep up with things in EE Times.

This morning's paper has a story about "private equity" firms being interested in investing in Cadence: Cadence would offer buyer steady cash flow. And, an investing blog has Cadence Design Negotiates With Buyout Firms.

This is all at the rumor stage, but it's interesting in what it says about EDA. Rather than being a high-growth industry where one might make several times investment by picking the right hot technology, this is more about lucrative cash flows coming from software maintenance agreements.

If private equity firms become players in our industry, how will this change them? Will it lead to "slash and burn" of R&D, just trying to milk the recurring revenue from existing products? But how could such an approach fund the R&D to keep pace with the changes and challenges following from Moore's Law?

Update: An EE Times blog posting on dynamics of the EDA business. And, a YouTube interview with Gary Smith and his DAC preview. EDA gets hip!

More Updates: Richard Goering weighs in.

DAC Linkfest

Last year, I went to DAC in San Francisco, and I made a number of posts to my blog both before and after the 2006 conference:

• DAC is Here!
• Gary Smith's Must-See List
• Cooley's Must See List for DAC 2006
• 2006 DAC Report

This year, I'm not going to DAC in San Diego, but I thought I'd at least "phone it in" for my blog. With due credit to the EE Times' Richard Goering and other professional journalists, here's your one-stop 2007 DAC blog nexus:

• What's coming up for DAC. Less DFM & ESL hype, more functional verification, STA, and low-power.
• 40 new exhibitors at DAC
• Missing in action at DAC 2007
• A "what's hot" list for DAC 2007
• DAC & DFM – Once More, with Feeling I can't tell who the author of this article is. But judging by the site and the length of the article, I think it must be "EDA Penny".
• John Cooley's DAC Cheesy Must-See List. John hasn't posted his list as of this writing, but it should appear soon at his DeepChip web site.

Existentialist EDA

I'm getting tired (so tired! --Bauhaus) of waiting on vendors who promise that all our problems with their product will be fixed in the next release!

I told an EDA vendor that waiting for their tool to improve reminded me of the play Waiting for Godot. I thought this quite clever, but they didn't seem to. Maybe they didn't have to read it in college?

It might be fun to cast EDA persons into the play. Who would play the roles?

Vladimir

The tramp who struts about stiff-legged due to a painful bladder condition.

Estragon

The tramp who complains of his ill-fitting boots

Pozzo

cruel but lyrically gifted man

Lucky

servant

The Boy

messenger

Godot

?

Here's my literary interpretation:

• Clearly, Vladimir and Estragon are the afflicted customers.
• Pozzo is either the sales or marketing guy (I often forget the difference).
• Lucky is the poor FAE.
• The Boy is post-sales support.
• Godot is ??? Hey, I don't have all the answers, use your imagination!

Something Completely Different (but Worthy)

Dear readers,

Off topic, though perhaps a reason for the decline in my posting frequency since the beginning of the year. For the past several months, I've been supporting a program that raises awareness and funds for The Leukemia and Lymphoma Society. This charity funds blood cancer research and patient services.

The program I'm part of is called Team in Training. Every season of every year, hundreds of runners, cyclists, and triathletes come together to train for a signature endurance event (e.g., marathon, century ride, or triathlon). More importantly, we collectively raise hundreds of thousands of dollars to help find a cure for cancer and to help those currently afflicted. We do this by getting sponsorship donations to the Society from our friends, families, and colleagues. Why not give blog readers a chance to help, too? That's where you come in. If your curiosity is piqued, and you'd like to read the rest of the story and perhaps make a donation to a very worth charity, please take a look at my Team in Training page. There you will find a link to another blog I've been keeping, "New Rider on the Purple Stage", which describes my cycling season in pictures and words. Please note that my season culminates in a few weeks, and the last day for donations for this season is May 21, 2007.

Thanks for reading.

John

Executive Blogging

As seen on Dilbert.com:

Pretty funny, but hopefully not prevalent in our industry. For example, I recently started reading Jonathan's Blog by the CEO of Sun Microsystems, and it's pretty substantive and useful.

What's Special About This Number?

What's Special About This Number? was featured in IEEE Spectrum. It's an interesting list of factoids for past, present and future fans of mathematics.

Enjoy!

"How-to" SPICE Book

It's been several years since I've run SPICE myself, but I'm finding it increasingly needed even for a RTL/gate-level engineer. Could anyone recommend some really good SPICE books, which aren't just a reference but show you how to do things? You can post your recommendations and advice here as comments. The "things" I'd be most interested in doing would be characterizing digital standard cells and analyzing IC interconnect.

I looked at Amazon.com and didn't find a lot of books like this (no "SPICE for Dummies"?), but these two look interesting. Before I or my company spends a chunk of change, do you know these titles and how useful they are?

Legend of Test

Peggy Aycinena did a fine interview with Tom Williams, truly one of the giants in the field of Test. The guy invented full-scan DFT in the 1970s! Can you believe that? It's remarkable that his career spans 40 years, and he's been productive throughout. He's published many seminal Test papers, and has received the "Best Paper" award at DAC.

Be sure to go to the last page and see a list of his self-selected most important papers.

Hither ASIC

q.v. my earlier posting Whither ASIC, EE Times just ran a story on the declining activity in the ASIC business.

It's a thorough survey of what's happening in the business. I agree that designs need to see more IP reuse -- the extreme case is to use an ASSP. And I'm skeptical of Structured ASIC, and it seems the market has also given that idea the thumbs down. But the article didn't mention the trend of more fabless companies finding ways to do COT rather than ASIC design, possibly through "virtual ASIC vendors" like eSilicon or Open Silicon.

Intel to Build Fab in China

"Our goal in China is to support a transition from 'manufactured in China' to 'innovated in China'"
--Intel CEO Paul Otellini

Ah, globalization!

Whither ASIC

I'm surprised by how bad of shape the traditional ASIC business is in. Are any companies making money? Only IBM Microelectronics?

Several of the Japanese semiconductor powerhouses are cutting way back (or closing) their US ASIC engineering. Today a friend told me that LSI Logic isn't doing ASICs any more! Is that right?

The vendors that are doing the best have attractive IP portfolios, like IBM or TI. Those that historically relied on manufacturing process (e.g., Japanese) and left IP entirely up to the customer aren't faring well.

I'm especially surprised that even fabless chip startups aren't using ASIC vendors! They invest in the COT model or the "virtual ASIC" model, contracting with a number of service providers. I would have thought that the integration value-add of ASIC vendors would be even more attractive in these days of worrying about signal integrity, variability and DFM. Don't chip designers want "one throat to choke" when things going wrong?

We may not have ASIC vendors to kick around for long.

Britney Spears guide to Semiconductor Physics

Here's some fun on a Friday. EE Times gave me the link to this crucial technical reference, Britney Spears guide to Semiconductor Physics - The physics of optoelectronic technology . The material is technically sound and more accessible than a textbook.

Check it out if you don't mind gratuitous pictures of Ms. Spears. What's next, Paris Hilton's analysis of the Traveling Salesman Problem? (a Hilton ought to help with that ;-)

Immortal, Indeed

Those of you who read the print edition of EE Times may recall a funky little contest/feature that ran at the back of the paper, "Immortal Works". I think I can remember this *always* being part of the paper, even going back to the 1980s. Here's the latest version I could find.

Last month, EE Times went through a redesign. There are many changes to the organization and layout of the paper. It's actually printed on smaller (shorter and narrower) paper than before, in line with several major mainstream papers. More cost reductions from the ink and paper crowd, probably. I actually like the smaller format -- it's easier to carry around and peruse at opportune moments.

But I won't like if Immortal Works has been canned! It's missing from the redesigned print edition! According to the editors' explanation The new EE Times: more than a redesign:

Taking a hiatus will be Immortal Works, our longtime caption-writing contest of which many of you are devoted fans. We're moving the feature online, where the audience interaction is fast, efficient and easy.

Like I said, it was a sort of goofy feature. And even though I never had the time (or more likely, the wit) to submit an entry, I miss this quirky part of EE history! Immortal Works, where art thou?

Standards? EDA has lots of 'em!

While I'm pleased that the UPF power standard plans to converge with the rival Common Power Format (CPF), it begs the larger question: why should we have multiple standards organizations, anyway? I'm referring to Accelera, Si2, and the IEEE. It seems just the IEEE should be enough.

It's like professional boxing, where there are now so many sanctioning organizations (WBA, WBC, WBO, IBF, ...) that the average person has no idea who the real champions are, and no longer really cares, either.

CAD Engineer's Bookshelf

Inspired by the DFT Bookcase over at the DFT Digest blog, I decided to create pointers to the technical books I use every day in my work. (Yes, I looked the ones strewn about my desk and next to the computer, rather than those arranged neatly (and less used) on my bookshelf. Perhaps you'll discover a title or two that will help you.

	Great book for learning Perl -- it's how I learned, going through it from cover to cover. And I still use it for a basic reference.
	A surprisingly useful book. I can't count the number of times that I needed to solve some puzzle in Perl, and found it already grokked in this book.
	Lots of good ideas here. When you are going to pick a coding style, why not follow what they've already figured out?
	My newest addition. I'm enjoying working through it to learn about references, packages, and object-oriented Perl.
	Programming Perl is the "bible", though personally it's not my favorite. And I find Larry Wall's humour distracting.
	My go-to book for Tcl.
	Because, sometimes, a good ol' shell script is enough.

Ambric Multi-Core Design Wins Award

I like this press release: Ambric Wins In-Stat's 2006 Microprocessor Report Analysts' Choice Award for Innovation because of two eye-catching features:

• the claim that this multi-core design was first architected for easy programming, before creating the hardware architecture. I agree with the claim that "most massively-parallel chip companies started with the hardware, leaving the programming model almost as an afterthought".
• the implementation is globally asynchronous, locally synchronous (GALS). Man, that is sexy! ;-) I've been interested of commercial implementations of this more-efficient clocking approach.

I'm going to watch for Ambric and try to learn more about their designs. By the way, interesting caveat in the quotes: "If Ambric's tools work as well as the company promises, ..." Ain't that always the challenge?

That’s OK, the Corporate Raider took my backpack

Jonathan David is an active IEEE volunteer and he's the local chair of PACE, the career-oriented part of IEEE. He's written a nice post on career planning, Professions of a Silicon Valley Double-E: That’s OK, the Corporate Raider took my backpack. [on keeping your parachute ready].

It's a nice short read. One of the "takeaways" from his advice is that he highly recommends this book, which is surely a classic in career planning:

A Taste of DesignCon

I didn't go to DesignCon, but Gabe did, so let's sample his DesignCon Morsels.

What's nice is the variety of topics he touches on:

• The lack of interest in ESL vs. design implementation, and why engineers are being short-sighted by not getting into architecture.
• Thermal performance, an interdisciplinary problem. When I've been involved in thermal analysis, the biggest problem is coming up with a credible power consumption figure. It's back to the "vectors" problem, and what's a representative (or worst-case) simulation?
• Is DFM for Designers?
• Fewer students are going into Engineering. And engineers "get no respect", as Rodney Dangerfield would say.

Thanks Gabe, for the synopsis!

Dr. Thomas W. Williams to Receive EDAA Lifetime Achievement Award

Saw this over at DFT Digest: Synopsys Fellow Dr. Thomas W. Williams to Receive EDAA Lifetime Achievement Award

Look at all Dr. Williams' achievements, stretching back to the 1970s. This is (one of) the father of LSSD, which begat the full scan DFT methodology that we all use today. He's truly a giant in DFT one of the legendary early figures in EDA.

Congratulations on a well-deserved honor!

Chips Grab Mainstream Headlines

I was surprised and excited to see a chip-process development featured on the front page, above the fold, in the San Jose Mercury News. This is "the newspaper of silicon valley", as they say. The headline gushed Chip advance biggest in 40 years.

It's about successes announced by Intel and IBM to fabricate metal-gate transistors with "high-K" dielectric. This is good news, which hopefully will enable us to continue to follow Moore's Law.

But it doesn't hit me that this is the biggest development in 40 years. Is this triumph over materials significantly different from figuring out how to to use Copper interconnect, or "low-K" interconnect isolation? Those were both hard manufacturing problems that the process wizards solved in the last decade. Maybe it was a slow news day. ;-)

Is Texas Instruments Exiting the Semiconductor Technology Rat Race?

SeekingAlpha is a financial web site that I just discovered. It's unique in that it focuses on analysis rather than news. And I've started following semiconductor company analyses, such as Is Texas Instruments Exiting the Semiconductor Technology Rat Race?

Technologists live for working on leading edge technology. TI killing off 32nm development is a major change in how it views itself and whether it will be able to attract the best and the brightest scientists in the future -- not to mention how the ones who do this there today must feel.

Now that is significant! Another IDM "throws in the towel" on doing all their own process and fab development. Will we be catching our breath at 45nm for awhile?

Yahoo! EDA!

Does Yahoo! understand the EDA industry? I have the headlines from their EDA News News Archive - Yahoo! Finance in "My Yahoo!". But most of the time, even a very liberal definition of "EDA" doesn't explain why these articles are here. I can understand including foundries, IP vendors, and even programmable logic companies. But how to understand the inclusion of U.S. Department Of Commerce Makes Annual Adjustments to Seasonal Factors for ISM Manufacturing PMI and Diffusion Indexes and ISM Non-Manufacturing Diffusion Indexes or Roche Diagnostics and Protedyne Sign Global Agreement?

I thought these industry news groupings have a human editor, but it makes you wonder ...

Intel Builds 80-Core Chip

This Intel 80-Core Chip is pretty far off in Research-land, but it does pose intriguing concepts, such as

• Better performance/power ratio
• Finer granularity of compute power and power consumption. If you need more performance, it wakes up more cores, and when you're done, they go back to sleep.
• "Core hopping". If one part of the chip gets hot, the work that those particular cores are doing is moved to other cores on another part of the chip.
• On-chip communications network. Of course, all multi-core chips have some sort of network. I'd like to see how sophisticated the Intel one is.

Prof. Richard Newton's Influence on the EDA Industry

Lamentation & Loss is a enlightening eulogy for Professor Richard Newton. By interviewing several EDA industry legends, Peggy Aycinena succeeds in recognizing Prof. Newton's profound impact on EDA, and reveals interesting history about Cadence and Synopsys, among others.

Hewlett-Packard's FPGA research, and replacing transistors

You may have seen the story earlier this week about a "breakthrough" announced by HP researchers, which involved applying nano technology to semiconductors.

I was intrigued, and Googled around to find this analysis at the "ars technica" web site: Hewlett-Packard's FPGA research, and replacing transistors. This excellent article explains that the HP announcement is for a very specific (and limited) application: FPGA interconnect. And it points out that the more promising HP announcement actually came out in 2005, which pointed to use of nanotechnology for circuit switching, not just interconnection.

Gotta love this web site's tag line: Serving the PC enthusiast for over 6x10^-2 centuries!

Best Companies to Work For ASIC & EDA?

In the news today is the much-talked-about list of 100 Best Companies to Work For 2007 in Fortune magazine.

Hmmm, the companies that we typically work at didn't fare too well. I only see a couple that would typically have ASIC or EDA engineers:

11

Cisco Systems

14

Qualcomm

87

Texas Instruments

As far as high-tech, there are a lot more software companies listed, and many related to health care.

It would great if EE Times did an industry-specific version -- Best Places for an EE to Work For!

DAAMIT vs. ChipZilla, Past, Present and Future

I've mentioned this tech enthusiast web site before. Geek.com Geek News - Is AMD's vision enough? is a great summary of the multi-core strategies being pursued by AMD and Intel. Be sure to check out the User Comments, which are one of the best resources of this site. "GoatGuy" is the real deal, always good for expert commentary. And this lexington_steele guy is pretty provocative, too. I wonder where he got that name?

R.I.P. Dean Newton

The EDA industry and the University of California lost an influential leader with the passing of the College of Engineering Dean, Richard Newton: EDA icon Richard Newton dies.

I was fortunate to hear Dean Newton speak at a "Berkeley in Silicon Valley" lecture last April. My notes from that lecture note that "synthetic biology", the application of engineering to living organisms (on a nano scale), was one of Dr. Newton's current passions, and his family requested donations in his name to the Berkeley Center for Synthetic Biology.

Update: John Cooley's Memories of Professor Richard Newton.

Happy New Year in ASIC & EDA

I thought about writing a forward-looking article, making some predictions about our industry. But, so far, I am too lazy. ;-) Besides, that's what Gabe & Gary get paid the big bucks to do. So, here are links to their New Year columns with a bit of color from me.

• Gabe's column, Last minute deals open opportunities for 2007 and beyond, is focused and sounds plausible. His DFM story sounds good -- it needs to get more into the design phase, as a proactive guide to help people laying out the circuits. And I like his call for "Locality Sensitive Cells" that would be DFM-correct by construction. His other point, about Mentor's moves in the ESL and C-synthesis space, discusses alternatives to SystemC, and where C may be lacking as the perfect system-level language.
• Gary's "column" isn't really written by Gary. He has Richard Goering as his ghost writer! I have more problems with Gary's predictions that Gabe's. Gary is still predicting the ascendancy of ESL, FPGA, and embedded software. I still see plenty of challenge and opportunity in plain old RTL-based standard cell design! Gary does have 10 predictions, and it's worth looking over the rest of them for thought-provoking variety.

Get a (better) job

I've been reading Ask The Headhunter for years, since Nick Corcodilos wrote a column in EE Times. It's always provocative, and worth a read if you may be looking to get hired or do some hiring in the future. (And who isn't?)

Poke around his web site to get a feel for what he writes about. It's a good reference. And, sign up for his newsletter to get his periodic thought-provoking missives. Happy Holidays!

EDA is Child's Play

One of the more common parts of my job is to figure out why something stopped working, or why it is suddenly producing different (namely worse) results than before, when "nothing's changed". Things like

• Why is the synthesis tool crashing now when it ran fine before?
• What changed so that I'm not making area/timing any more?
• Why is equivalence checking failing now?

For all of these sorts of things, I end up comparing logs, netlists, scripts, etc. I am the tkdiff master! With my eagle eye and understanding of the personalities of EDA tools and companies, it's a sleuthing challenge to find the culprit.

If I tried to explain this to a layman, I'd have to say that part of my job is playing the grown-up version of one of my daughter's favorite games, Spot the Difference. Yes, that's what I went to all those years of college for. :-)