- the claim that this multi-core design was first architected for easy programming, before creating the hardware architecture. I agree with the claim that "most massively-parallel chip companies started with the hardware, leaving the programming model almost as an afterthought".
- the implementation is globally asynchronous, locally synchronous (GALS). Man, that is sexy! ;-) I've been interested of commercial implementations of this more-efficient clocking approach.
I'm going to watch for Ambric and try to learn more about their designs. By the way, interesting caveat in the quotes: "If Ambric's tools work as well as the company promises, ..." Ain't that always the challenge?
1 comment:
Asynchronous processor?
Will they be able to extract maximum performance from a "system" which has fully synch clocks? Especially given all the various tricks (like RDRAM's two transfers per cycle features).
Interesting development none the less - I was interested in this academically at one point in time.
Post a Comment