The power reduction is through a three-pronged attack:
- Increasing treshold voltage. This is familiar to all nanometer-scale digital IC designers today.
- Low Damage Junction Engineering. Uh, that's some real process engineering, and I don't have much insight.
- Increased Gate Oxide Thickness. This is very interesting and counter to scaling and performance trends. But, when the gate oxide is only 3-5 atoms thick, you have to question "how thin is too thin?". The article just mentions making the oxide thicker. Presumably this is less risky than utilizing often-mentioned but not-in-production High-K Dielectrics.