Intel's Ultra Low-Power Process

There was a story a couple of days ago about Intel announcing an ultra-low power 65nm process. I've been looking around and couldn't find much technical detail, but New Intel 65 nm lithography promises reduced leakage for small devices at Tom's Hardware Guide has the most detail.

The power reduction is through a three-pronged attack:

1. Increasing treshold voltage. This is familiar to all nanometer-scale digital IC designers today.
2. Low Damage Junction Engineering. Uh, that's some real process engineering, and I don't have much insight.
3. Increased Gate Oxide Thickness. This is very interesting and counter to scaling and performance trends. But, when the gate oxide is only 3-5 atoms thick, you have to question "how thin is too thin?". The article just mentions making the oxide thicker. Presumably this is less risky than utilizing often-mentioned but not-in-production High-K Dielectrics.