Tuesday, September 20, 2005

Startup claims FPGA lead with asynchronous logic

EETimes.com - Startup claims FPGA lead with asynchronous logic one of a handful of claims for products based upon asynchronous logic design.

I'm very intrigued by this idea. It has the promise of removing lots of overhead in chips for clock distribution and balancing. Not only does all the synchronous clock overhead use a significant amity of chip area, but it uses up a large amount of the standard cell power consumption! Every one of those clock buffers toggles twice per period, giving it a "toggle factor" of 2X.

I don't recall asynchronous logic design being taught in any of my engineering classes. There need to be more resources to learn about it.

Another big roadblock is that there is not the EDA infrastructure for asynchronous design. All the commercial synthesis, timing, and test tools assume synchronous design.

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