Thursday, July 28, 2005
Wednesday, July 27, 2005
I'm very curious about how front-end or RTL design can influence manufacturability or yield in a Standard Cell flow. I don't see the connection.
Improving yield in RTL-to-GDSII flows sounds like it would explain it all for me, but the connection to RTL design still seems to be missing. I see where synthesis might be able to select cells out of a "high yield" library (if such a beast existed), and certainly there are things to do during routing, such as adding redundant vias. But this is all physical design. Is the logic designer off the hook?
- Signal Integrity
- Visualizing the behavior of Logic Synthesis algorithms
Some of the other papers are more oriented to Magma tool capabilities, but because their tool suite is modern and novel, they should be informative as well.
Wednesday, July 20, 2005
Monday, July 18, 2005
Interoperability plays a key role in elevating designers to a higher level of productivity, just as Tenzing Norgay's efforts facilitated the first ascent to the top of Mount Everest, said Rich Goldman, vice president, Strategic Alliance at Synopsys.
Ah, it all makes sense now. ;-)
- Managing power
- Managing the memory bandwidth bottleneck
Here for the foreseeable future is a world of parallelism, of increasingly application-directed architectures and of an unending struggle for memory bandwidth rather than Mips.
Monday, July 11, 2005
- How do they know what IP to diffuse onto the base layers? How do you reconcile if one customer wants N Serdes macros, and another wants M megabits of RAM?
- Who is really using Structured ASIC? How real is it, and for what applications?
Thursday, July 07, 2005
- The argument for "scaling out" is similar to NVIDIA's SLI strategy, which links two GPUs to work in parallel on graphics rendering.