LSI Logic RapidChip & Structured ASIC

I've always been intrigued by initiatives to bring down the ever-increasing cost of nanometer-scale IC design. While mask sets can cost more than $1M, I fondly remember the days of Gate Array vendors' ability to turn prootypes in less than a week! LSI Logic's Leverage reads like a PR piece written by LSI Logic about RapidChip, their Structured ASIC product. While intrigued, I want to understand about these technologies:

1. How do they know what IP to diffuse onto the base layers? How do you reconcile if one customer wants N Serdes macros, and another wants M megabits of RAM?
2. Who is really using Structured ASIC? How real is it, and for what applications?