I'm very curious about how front-end or RTL design can influence manufacturability or yield in a Standard Cell flow. I don't see the connection.
Improving yield in RTL-to-GDSII flows sounds like it would explain it all for me, but the connection to RTL design still seems to be missing. I see where synthesis might be able to select cells out of a "high yield" library (if such a beast existed), and certainly there are things to do during routing, such as adding redundant vias. But this is all physical design. Is the logic designer off the hook?