The Intel Development Forum got tons of press. Intel is running away from the "most gigahertz" school of CPU design because of the stifling problems of power management. I'll link the best articles with IDF coverage here:
Monday, August 29, 2005
Update: this article in BYTE magazine (subscription required) describes how Intel really wants programmers to write parallel code.
This EE Times report from the Hot Chips conference, NVIDIA scientist calls for expanded research into parallelism, raises one of the "dirty little secrets" of all the hype about multi-core CPUs -- it is hard to make applications multi-threaded! Do we already have a good programming language for describing an application's parallelism, or is a new language needed?
Meanwhile, those working in the graphics arena are ideally suited to taking advantage of Moore's Law:
Kirk contrasted this situation against the entirely different structure inside the GPU. "Graphics has been called embarrassingly parallel," he said. "In effect, each stage in our pipeline, each vertex in the scene and each pixel in the image is independent. And we have put a lot of effort into not concealing this parallelism with programming."
This allows a GPU developer to simply add more vertex processors and shading engines to handle more vertices and more pixels in parallel, as process technology allows. "We are limited by chip area, not by parallelism," Kirk observed.
Thursday, August 25, 2005
Each of these contains more transistors than an AMD Atlon64 CPU. There is a lot of power (both computing and electrical) in these chips!
Tuesday, August 23, 2005
I like the article more for this history than any insight I have into their new router's prospects. Also very impressive is the amount of money that Cadence paid to acquire CCT. It would be really interesting to do an analysis of what EDA vendors have paid for acquisition, and what returns they got. How about Cadence's acquisitions of Ambit and HLD Systems? HLD in particular didn't see to last long.
Thursday, August 18, 2005
Tuesday, August 16, 2005
Constructing the next transistor , in EE Times, is a superb article describing the technical challenges to building useful transistors below 65nm. It covers the physical and materials challenges that are arising, and how the solution to one problem (e.g., low leakage power) may aggravate another (high performance).
I'd love to have seen this illustrated with some pictures -- I wonder if the print edition has that? In any case, if you're a semiconductor engineer or scientist, you'll find this article worthwhile.
Why, it even makes me want to dust off my semiconductor textbooks to remember what's really going on inside a MOS transistor!
Tuesday, August 02, 2005
I admit I'm not a financial guru, but trounces seems like a strong word for "Cadence recognized net income of just $500,000, or $0.00 per share"!
UPDATE: Synopsys will announce their 3Q2005 earnings on August 17.
- Cadence Trounces Guidance Again
- Magma Reports Fiscal Q1 Sales Up 8% The fourth largest EDA tool supplier reported record high revenue of nearly $39 million for the fiscal quarter ended July 3.
- Mentor Q2 Sales, Earnings Fall Due to lower than expected bookings, the third largest EDA player saw both revenue and earnings per share fall, but remains positive for future growth for new and emerging products.