The Dangers of Living with an X (Bugs Hidden in your Verilog)

The Dangers of Living with an X (Bugs Hidden in your Verilog) is a technical paper that is important for ASIC design and verification engineers. It's an exhaustive analysis of interpretation of the 'X' value in Verilog HDL. This detail is often misunderstood and can be dangerous in design. The paper was originally presented at SNUG. It says the author won the Technical Committee award. I'm surprised he didn't win additional awards -- it's one of the best ASIC design papers I've read.