I'd like to to wish you all very happy holidays, however and wherever you celebrate them. With the recovering economy, may we all have a happy and prosperous 2010.
Wednesday, December 23, 2009
Thursday, December 03, 2009
It's hard to imagine greater evidence of a tremendous impact on computer science than authoring the most cited paper in all of computer science as well as in EDA. Remarkable! Before you follow the links, can you guess the subject of the paper?
Tuesday, December 01, 2009
The original player in this market was Interra Systems. A great schematic front end is GateVision, available from Concept Engineering. Are there any other major infrastructure providers I've overlooked?
Friday, November 13, 2009
Now I read Tech layoffs continue, despite signs of economic improvement and it makes me feel my prior observations are the exceptions to the rule. What's your sense of the current job market? I'm hoping that my new found pessimism represents "capitulation", that point when hope is lost, and marks the nadir of a market or trend.
Friday, October 30, 2009
Tuesday, October 06, 2009
When I'm out and about doing chores or exercising, chances are I'll be listening to my iPod. But more often than not, I'm listening to podcasts rather than music. Listening to podcasts is an efficient way of "reading on the go". You can catch up on the latest news stories, political opinions, or investment ideas. Those are my interests; you can find a podcast on practically any topic.
Have you listened to podcasts? Which are your favorites? In our field of semiconductor engineering, there's not a wealth of content. But here are some of my favorite engineering/technology podcasts to get you started.
- IEEE Spectrum Podcast, which is described at Podcast Picks.
- Science Friday by Ira Flatow. A classic high-quality program from NPR.
- Security Now by Steve Gibson and Leo Laporte. It's mainly about computer security, but you can also learn the latest on PC software and networking by listening.
It's easiest to subscribe through iTunes, but there are other ways using the RSS feed and a "podcast catcher" program. Happy listening!
Tuesday, September 29, 2009
Why am I bringing this up now? Because the Synopsys Users Group - San Jose Call for Papers is open! Here's a chance to show your chops and burnish your resume by demonstrating the cool stuff you're doing with Synopsys tools. The authors get a lot of support from the experience Technical Committee [full disclosure: I'm a member] to help develop their presentations and papers. Think about it, and I'll see you at SNUG.
Monday, September 21, 2009
How's the Market?
What's your perception of the ASIC/EDA jobs market? My take is that it's pretty weak, but a number of companies are "selectively hiring". I had a couple of friends leave their struggling design services firm, and they were able to land jobs at established growing companies within a couple of months. On the other hand, there are plenty of engineers who have been looking for many months.
One differentiator is that hiring favors leading-edge experience (e.g., expert P&R and design closure of 65 or 45nm chips), or knowledge (e.g., advanced degree with an emphasis on an emerging hot area).
Natives Say No
With the depressed job market, this isn't the best time to wonder about this, but I'm perplexed at the lack of US-born chip design engineers. Of course, it stems from the lack of US-born engineering graduates. This leaves me scratching my head--engineering jobs are not THAT bad. As a matter of fact, they're one of the fastest ways to earn a very good paycheck out of college, with intellectual challenge to boot.
A downside is that engineering isn't the most secure career around. There are regular risks of downsizing or technological obsolescence. It's not a cushy career, but how many are in this age of globalization?
If you want a secure career, at least medicine and law are "less outsourcable". However, if you really want societal respect, security, and a guaranteed comfortable retirement, I recommend becoming a fireman.
Give US Your Best and Brightest
In the US, we are so fortunate to attract many of the best and brightest scientists and engineers from the rest of the world. There can be complaints about "H-1B abuse", but there needs to be a system that allows the country to benefit from the great contributions possible from immigrants with advanced degrees.
Where Do Seasoned Engineers Go?
While I'm not there yet, friends and I do wonder where all the full-career engineers are. Look around you -- do you see many 50-something engineers? I don't, and I wonder. Do they all transform into real estate agents? Or should I worry about a future as a Walmart greeter?
Others Weigh In
- As I was preparing this post, a timely and provocative article appeared in EE Times, U.S. engineers at a disadvantage . The discussion in the comments is fascinating.
- Update: Harry the ASIC Guy and his commenters weigh in on outsourcing, and IBM's aggressive program in particular.
- Update: Lou Covey has analysis and advice at We're in this boat together. Start acting like it.
Monday, August 24, 2009
Back before "nanometer design", there was "deep submicron design", and ASIC synthesis users became very concerned about interconnect effects on timing. The first attempt to deal with this was through "Links to Layout", and especially a whole slew of custom wireload model (CWLM) strategies. If you look at SNUG programs a number of years ago, there were more CWLM papers than you could shake a stick at.
A major advance in accounting for interconnect effects was when synthesis tools started to perform "virtual layout" as part of the optimization-estimation-timing analysis loop. The most notable tool to do this was Synopsys Design Compiler Topographical. My colleagues and I did evaluations of DCT starting with 90nm designs, and data indicated better correlation and generally a better netlist for Place & Route.
As we progress from 90nm to 45nm and below, physical considerations are becoming ever more sophisticated. The latest examples are
- Synopsys Design Compiler Graphical. Includes congestion prediction and some congestion relief algorithms.
- Cadence RTL Compiler's New "Spatial Technology", the latest physically-aware RC feature.
- Oasys RealTime Designer. "RTL physical synthesis."
The Skeptic Weighs In
While "getting physical" has the feeling of more accuracy and general goodness, TNSTAAFL. Though I hope for better quality of results and predictability, I see the following drawbacks
- It forces the logic designer to learn physical design details, and learn new tools or coordinate with a physical designer. While that's nice to know, it takes away from the RTL creator's time to focus on architecture, design and verification.
- The optimization process itself will either take longer (to perform the "virtual layout"), or results will be less-optimal, because optimization time will be taken away in order to run physical algorithms.
- Some of the effort may be wasted, especially for detailed buffering and gate sizing. For example, some P&R tools "throw away" the incoming netlist's buffering and sizing, and re-optimize in the physical domain. So, that effort in logic synthesis is wasted (other than its predictive benefit).
- While WLM-based synthesis is well understood and mature, these physical tools are not. It may take a long refinement period for the tools to produce reliable netlist quality and consistency.
- Some of these tools can't decide if they're logic design tools, physical design tools, or some mish-mash of both. In their efforts to be accessible and affordable for logic designers, they may lack the physical design functions and data access needed to do the job right.
Over the coming months, advanced synthesis users will be putting these latest tools through their paces with real designs. And we'll start to learn whether the added complexity and cost leads to better implemented designs. If not, we can always go back to our old friend the wireload model, trying to get to P&R quickly, where the rubber really (not virtually) meets the road.
Update: I stumbled upon a detailed reply/rebuttal over on the Cadence Logic Design blog! Jeffrey Flieder, thanks for writing this. I very nearly overlooked it.
Friday, August 07, 2009
My pre-DAC post Looking Forward to DAC laid out what I hoped to investigate by visiting exhibitors, namely
- Low Power
- Asynchronous Design
Well, despite my best-laid plans, I wasn't able to check all these items on my list in two days of roaming the exhibits floor. In some cases (i.e., Asynchronous Design), I didn't find an appropriate vendor. In other cases, my schedule or the vendor's appointment constraints didn't allow me to gather the information. But DAC was a great opportunity to see many vendors, and by careful plan or happy accident, I was able to visit many interesting companies. I'll group my vendor impressions into these categories:
- It seemed like Oasys Design Systems was the most talked-about implementation vendor at the show. As I've said before, their capacity and run time claims are incredible.
At this show, they put a lot of emphasis on making their claims credible.
They've got some customer testimonials to validate them,
and their closed-door demo suite explains what's revolutionary about their physical synthesis approach,
and why it could be dramatically faster than today's synthesis tools.
Harry the ASIC Guy explains technical details of Oasys' approach.
And to top it all off, I just about ran into Joe Costello on the DAC floor. (He was suspiciously near the Synopsys booth at the time.) It should be great to have Joe back in the EDA industry. I like and respect Aart de Geus a great deal, but Joe Costello can add motivation and excitement back to an industry that's feeling tired.
- Micro Magic is an interesting small design/tools company that's been around almost 15 years.
Because DAC wasn't very crowded on Wednesday, I could walk into their booth and have a long
informal chat with their CEO.
He exudes confidence and credibility.
One of their tools is a Datapath Compiler, which is one of the few commercial solutions for maximum performance datapath design. Other companies have come and gone (Arcadia is long gone; Arithmatica wasn't at DAC), but Micro Magic apparently has numerous real success stories. (Their customers seldom allow themselves to be named.)
- iNoCs is an early stage startup with tools to synthesize Network on Chip (NoC) IP. Their debut was especially timely because NoC was one of the technologies featured in the Wednesday Keynote by Bill Dally, Stanford professor and NVIDIA Chief Scientist. As it turns out, the connection is even stronger. iNoCs is advised by noted EDA professor Giovanni De Micheli, who has been a colleague of Professor Dally.
- The only company I met with a heavy focus on new parallel computing products was ACCIT, which is developing highly accelerated SPICE simulators running on ATI GPUs. Looking forward to the NVIDIA CUDA port, guys!
- Of course, many of the big EDA vendors are adapting their products for multi-core technology, for example Synopsys PrimeTime Multicore.
I spoke to a few vendors in this space, but I wouldn't dare pretend to have a good grasp on where the field is at. Several journalists and bloggers are writing "now is the time for ESL synthesis", but I have yet to meet the designers using it or even enthusiastic to get into it. It's puzzling to me. There apparently are specific domains with considerable success, such as wireless and image or video processing. And there are specific geographic areas adopting it first, namely Japan. But for the mainstream ASIC designer, I don't yet see it catching on.
I liked what I heard in a brief visit with Imera, which develops hardware+software solutions to allow secure remote debug of software (e.g. EDA tools). In my work, there is constant antagonism between the EDA vendor, whose engineers claims they cannot debug their software beyond their walls versus the EDA customer, which doesn't want the "company jewels" of full-chip RTL or netlists to ftp over to the EDA vendor. Imera has solved the problem with a distributed debugger and networking solution that allows the R&D engineer to debug from the vendor side, while the EDA tool is running on the design data at the customer's site. Sounds like it would resolve the stalemate and allow us to get on with the problem-solving.
I had not attended DAC since 2006. It was a little disorienting because of all the changes in the industry and the conference itself. Attendance was way down from boom times. For the first time, I had an "exhibits only" pass, which allowed me to go up every day and visit the exhibits floor but not the technical program. After Free Monday, the floor was much less crowded, and it was a pleasure to walk right up to any vendor and get all my questions answered. One irritating practice of several vendors was to not have any open demos, but to require a one-hour appointment to be scheduled for a closed-door meeting. I found this quite inconvenient for any sort of spontaneous discovery, and as a result both vendors and I missed out on some worthwhile discussions.
I was glad I attended DAC. I obtained information that will help me in my job, and met old and new friends. I wish for the sake of the organizers and the exhibitors that attendance had been stronger, but the economy was a strong tide to fight. Let's hope that tide is turning and the 47th DAC in Anaheim will celebrate a growing vital EDA industry.
Wednesday, July 29, 2009
If you're at DAC and haven't yet overdosed on "Social Media", please stop by Tweet, Blog or News: How Do I Stay Current? this afternoon. I'll be on the panel, sharing ideas for how to wade into this trend in the most efficient way. Listen, ask questions, and say Hi.
Denali Software is a great supporter of DAC. They teamed up with Atrenta and Springsoft to start the I Love DAC program and provide dozens of complimentary Exhibits passes for the conference. They also ran good-natured competitions for EDA's Next Top Blogger and EDA's Community Superheroes. Congratulations to Karen Bartleson of Synopsys for winning the Top Blogger distinction, and Joy Matsumoto from Cadence for her great efforts to support charitable causes.
Tuesday, July 28, 2009
DAC begins its second full day in San Francisco, and I encourage you to take advantage of the opportunity. I was up there yesterday and found a great variety of vendors, panels, and other events to check out. In the morning, crowds were pretty sparse, but there was a definite pick-up in the afternoon. In particular, there was a lot of congestion around the prominent Synopsys booth, next to a well-visited Standards area.
That said, I'd encourage everyone to venture out beyond the comfort and safety of the big EDA vendors! If anything, I de-emphasize visits to the top vendors, because one can follow their announcements and arrange meetings any time of the year. But DAC is a unique opportunity to see a great variety of vendors, from the "second tier" specialist that you're not quite familiar with to the Mom & Pop startup that just rolled out their shingle for their first DAC. To make this discovery more purposeful, I flip through the Exhibitor descriptions in the DAC program and highlight the booths of companies that sound remotely interesting. That way, you can avoid wasting time by ping-ponging between North and South halls. Go for it!
On a lighter note, on Sunday I made my way to San Francisco for an EDAC reception. Before that, I explored Golden Gate Park (stunning!) and snapped a few pictures.
The first perplexed tool user.
Monday, July 27, 2009
Caltrain provides service on the San Francisco Peninsula. Here's their schedule. If you catch one of the "baby bullet" express trains, it's less than an hour from San Jose to San Francisco. Fares from San Jose are
From the Caltrain station in San Francisco, you'll need to get to Moscone Center. In previous years, DAC ran a shuttle for this, but I don't see any notice of it this year. You can either walk or take the city bus. It's only a one-mile walk, so I plan to try this and count the back and forth as my exercise for the week. Google has a nice map showing both the walking route and links to bus schedules, if you prefer. View Larger Map
BARTBay Area Rapid Transit has stations on the Peninsula and East Bay (Fremont is nearest to Silicon Valley) and can take you to Montgomery Station, only 3.5 blocks from Moscone Center. The One Way fair from Fremont to Montgomery Street is $5.60.
Wednesday, July 22, 2009
As a pleasant surprise, there's quite a bit of activity and emerging excitement in the area of synthesis, just in time for this year's DAC.
It's exciting to hope for a revolution in synthesis. Put me in the "show-me" camp. It's (relatively) easy to meet 80% of what Design Compiler can do, but there are many features and tricks developed by DC over the years, making it a hard tool to displace. Synopsys has certainly seen strong competition, including from Ambit BuildGates (acquired by Cadence) and most recently by Get2Chip (now Cadence RTL Compiler). What often happens is not that king DC is overthrown, but that the competition lights a fire under Synopsys and their tools will improve at a much faster pace than market dominance would dictate.
What's interesting about Oasys are the tremendous claims about capacity and run time, and the emphasis on physical synthesis, combining logic synthesis with placement and optimization. The company also has impressive board members, including Sanjiv Kaul (former implementation GM at Synopsys) and, re-appearing to EDA after a long hiatus, Joe Costello (charismatic and successful former Cadence CEO).
For several years, EDA industry analyst Gary Smith has been calling for the ascent of ESL (Electronic System Level) design. He was already called an ESL evangelist back in 2006! It's been the next big thing for a while now. It seems to follow the industry's progression from transistors to gates to RTL, but RTL remains the mainstream design method.
In the context of design implementation, ESL implies synthesis at a more abstract level than RTL. This year, there appears to be considerably more buzz, and not just from Gary. See, for example, recent posts by John Cooley and Richard Goering.
Key players include
My apologies for any I've overlooked--I'm learning about this field. One point of concern is that there isn't a consensus on design language/dialect, which varies by vendor over C, C++, SystemC, and proprietary languages/extensions. That can impede adoption. It was Design Compiler that established the de facto standard for Verilog RTL synthesis subset, and this provided a common point for customers (and competitors) to converge on.
It's nice to see continued innovation in this critical area of IC design, and merits further investigation.
Monday, July 20, 2009
As most everyone is aware, the big conference in the chip design software world, DAC, runs July 26-31 in San Francisco. I'm looking forward to it and plan to be up there most days. Some prognosticators have posted their "must-see" lists. (Gary Smith, John Cooley laying out the law for aspiring vendors) and there will be more to come.
Rather than calling out specific companies, I'll share some of technologies that I'll be looking to learn more about.
- Low Power
- This is one of the genuinely valuable and necessary "next big things" in methodology.
- I've always been surprised that specialized datapath techniques aren't more successful. It seems like you either use an advanced RTL synthesis tool, or design datapath by hand. There's not a lot of in-between.
- MCMM (Multi-Corner, Multi-Mode)
- It sounds like the solution to many problems. But how well does it really work -- how scalable is it?
- parallelism, multi-threaded, multi-core, GPGPU
How will EDA ever catch up to designs scaling by Moore's Law?
By using the parallelism available in today's CPUs and GPUs.
Multi-core is working today for 4-8 cores, but may hit a wall beyond this.
And what about the tremendous parallel computational power in your
Graphics Processing Unit?
A few EDA tools are leveraging the CUDA platform; where will it pop up next?
Update: check out Richard Goering's interview with EDA luminary Kurt Keutzer on this topic.
- Asynchronous Design
- This is my token research-y interest. Synchronous design is what we all learn in school, and there's a plethora of tools (namely, the EDA industry) to automate such designs. But there are drawbacks with respect to area and power. Can we learn a new way to design, and develop new sets of IP and automation tools?
Friday, July 17, 2009
Don't believe everything you read. There's an insightful behind the scenes exposé on DeepChip about a technology web site that turns out to be a marketing venue for a group of EDA start-ups. Nothing wrong with that, but the disclosure of who's behind it took some digging and questioning to tease out.
Of course, one would be naive to assume this doesn't happen elsewhere in the media. Even Mr. Cooley's beloved DeepChip, with its purported user-generated content, can be gamed. When you read a glowing endorsement of an EDA tool, ask yourself questions such as
- Who wrote this? Are they "anon"?
- Did they really write it? Or could it have been "ghost written" by the EDA vendor and submitted in the customer's name?
- What is the author's interest in the vendor? Does the author's company have a financial or other interest in the vendor's success?
Nothing beats the testimonial of someone you know and trust, other than your own hands-on evaluation.
Wednesday, July 15, 2009
Over the years, DAC has become more user friendly. The panels in particular are often informative and sometimes provocative. I find that I'm getting more and more out of DAC.
This year, there's an explicit "User Track" at the conference. I'd like to share a description of the User Track while presenting the first guest post on John's Semi-Blog. Please enjoy!
User Track at DAC: Learn from Your Peers
46th DAC Design Community Chair
46th DAC New Initiatives Chair
Today’s connected world makes it possible for you to work from everywhere. Yet, there’s only one place where you can learn how your peers successfully applied design tools to chip design and where you can exchange valuable experiences: the new User Track at this year’s DAC.
The three-day User Track features 40 presentations that run in parallel with regular technical sessions. Speakers include expert designers from Cisco, ClueLogic, Fujitsu, IBM, Infineon, Intel, Qualcomm, Samsung, STMicroelectronics, Sun, Texas Instruments, Virtutech, Xilinx and others.
Identifying Front-End Challenges
Power planning and verification continues to be hot. A team from NEC will detail an automated flow to pre-characterize the power consumption of a set of basic components starting from their behavioral description in C, down to their power estimation at the gate-level netlist. A team from Cisco will describe the use of a power noise analysis tool to analyze system power integrity. Engineers from Texas Instruments will illustrate how they used an EDA tool to integrate complex multi-power/voltage domain design. Intel engineers will present a flexible, high-level power management modeling and simulation framework for power architects. And, a team from STMicroelectronics and ST-Ericsson will outline an exploratory and refinement-based power planning system. Also, Intel engineers from India and Israel will offer a novel direction for using abstract executable models to verify power management protocols.
Tackling Backend Challenges:
In the Practical Physical Design session, a team from Intel will discuss how they tackle ECOs as late logic changes delay the process and register arrays occupy more than half of all transistors of modern designs. Qualcomm designers will describe how they build their semi-custom methodology and STMicroelectronics engineers will outline e how they use the IP-XACT standard from Spirit to enable IP reuse.
Accurate power supply and substrate noise analysis remains a challenge, and practitioners from Qualcomm, IBM, Samsung and Kobe University will show how they attack the problem. Texas Instrument designers will show how to analyze blocks for reuse in multiple metal stacks. Intel engineers will highlight their approach to assessing design feasibility early in the process to avoid problems later.
A team from Stanford University, Rambus and Netlogic describes a way to tackle analog reuse as it becomes as important as reuse is in digital design. A group from Cadence and several Taiwanese universities will describe their approach to integrate MEMs in mixed-signal designs. Engineers from NXP and Magwel tackled the problem of analyzing substrate noise and will present their results in 90nm process technology. With complex circuits often needing an integrated approach to physical and electrical verification, a team from SysDsoft and Mentor describes how they accomplished this on their designs.
In addition, join us for an Ice Cream Social Wednesday from 1:30pm-3pm where 42 posters will offer an opportunity for you to mingle with other EDA tool users.
Access to the User Track is included with the full-conference registration. Or, register separately for the User Track and get access to the keynotes, in addition to the User Track. For more details, visit: www.dac.com. We look forward to seeing you in San Francisco.
For more information:
Publicity Chair, 46th DAC
Tuesday, July 14, 2009
Not only is the video entertaining, but it's a bona fide piece of EDA history. It's also worthwhile to reflect on the promise of Frameworks, still unfulfilled in EDA: seamlessly integrated multi-vendor tool flows. Well, at least it's job security for CAD engineers.
Monday, July 13, 2009
And, at the party itself, watch the show and vote for EDA Idols!
John also posted that the very popular "Free Monday" deal is coming back as well. Here's what his email described:
From: Bob Gardner [bobg=user domain=edac.org]
Please inform your readers that EDAC has decided to sponsor the return of "Free Monday" to DAC this year. If they want to take advantage of this "Free Monday" registration, your readers must go to:
and complete all four pages of the registration. On the THIRD page they'll find a newly added "Free Monday Exhibits" option -- they MUST check this box to get this special registration.
On the forth page they should see a web receipt with their unique bar code confirmation on it. They must print this entire page.
To enter the DAC Exhibit Hall on Monday, July 27th, the engineer must present a paper copy of his/her entire bar code page to the Advance Registration desk located in the North Lobby of Moscone Center.
See you at DAC, John!
- Bob Gardner EDAC San Jose, CA
As for me, I've already paid my $50 for the all-DAC exhibits pass. See you there. The buzz for DAC is heating up, so watch for more blog posts before the conference.
Friday, June 26, 2009
Thursday, June 25, 2009
Rajeev founded several significant EDA companies, was apparently out-manuvered in the board room at times, and is forthcoming with what he's learned about the EDA industry and building companies.
Tuesday, June 23, 2009
I glanced at a few presentations and was most surprised to see predictions of the resurgence of ASIC vendors (vs. today's popular "COT" model). I'm not sure I agree, but it makes a certain amount of sense. It takes a lot of tools, people, and expertise to implement 45 nanometer chips. The proposition is that if it is possible to cleanly hand off at RTL, then the chip designer can focus on functionality, and let an implementation house focus on the tricks and traps of nanometer-scale design closure. But that's a big if, to be confident that the hand-off is of a properly constrained and realizable design!
Wednesday, June 17, 2009
You could find kindred spirits of any interest available for text-based correspondence and enlightenment. I solved countless software problem (including both Windows and Linux) by searching through these groups. Who could forget groups like
Oh, and the flame wars! (I remember there was a character outraged over the Ottoman Empire who sought to cancel every post containing "turkey", which swept up Thanksgiving recipes, as well.)
The beginning of the end was when Web access took off, epitomized by "AOL newbies" pouring onto Usenet without regard to the collegial etiquette that previously existed. After AOL, there was overwhelming growth of users, which strained the scalability of worldwide discussion forums. Finally, the death knell: Spam. When I peek at Usenet groups today, they're full of the most crude and amateurish spam. It appears that posts are not run through filters as is all of our email, and this makes the noise/signal ratio unbearable.
R.I.P., Usenet. You were one of the forefathers of what we enjoy today through the Web, forums, IM, and social networking.
Tuesday, June 16, 2009
There's been some griping that there's no "Free Monday" this year. Instead, there's an all-days Exhibits Pass available for $50. To me, that seems like a very reasonable proposition. It remains to be seen if this will cause a significant drop in attendance, and if those who won't pay $50 are the ones EDA vendors need to see at their booths.
As the conference approaches, there will be a number of "must-see" lists, and I hope to compile my own. Right now, I don't have a very clear idea about companies to see. I do have some ideas about what may be hot, from my ASIC design implementation-centric point of view.
What Should Be Hot
- Multi-threaded & Multi-core software. Initially, these trails were blazed by startups such as Extreme DA and Sierra Design Automation (now part of Mentor Graphics). Now, all the major EDA vendors are working hard at either developing new products or retrofitting established ones. Richard Goering has had a number of interesting technical posts about how it's going at Cadence.
- Multi-Corner Multi-Mode (MCMM) analysis and optimization. This has also been talked about for a long time. It's always seemed like a good idea, but is becoming more critical at the most advanced processes and design sizes. A key question is how practical this is. What is the performance penalty to go to MCMM? Helping to solve this will be multi-threaded & multi-core software.
- Low Power. Of all the "next big thing" areas of EDA, this has struck me as the most real. There are several viable verification products based on simulation or static analysis. For implementation, there's combinational and sequential clock gating, multi-Vth optimization, and support for voltage and power domain design driven by UPF (or in Cadence's case, CPF ;-)
Ready for Prime-Time?
- I've been doing a lot of reading about variation, and various techniques to account for this. It's a fascinating new way to think about semiconductor performance. But, there is so much that needs to fall into place for statistical techniques to be used in production: tools, libraries, and a new way of thinking about design analysis.
Count Me Skeptical
- ESL. Maybe it's the market I'm involved in, where "QoR", especially performance, trump potential productivity gains at higher-abstraction design levels. This may be more attractive when time to market is everything and the QoR tradeoff not so great.
- RTL analysis & design planning. Again, maybe it's because of where I sit, but you can argue about getting too carried away with analysis at RTL. RTL is the functional description of the design. Implementation can be done "downstream" of that.
Tuesday, May 19, 2009
I've recommended Nick Corcodilos' Ask the Headhunter web site before for its unorthodox, yet sensible, advice to finding the best job for you. I'd recommend that you sign up for his newsletter on the web site if you like what you see. This week, he describes taking a Library Vacation(tm) for someone contemplating a career (not just job) change. It's an exciting idea!
I've seen a few friends leaving the high-tech industry, and their transition plans sometimes could use more rigor. It seems like everyone wants to get into a "green" or "alternative energy" job! I'm sure that will be big eventually, but it's better to expand your search space, and carefully consider what you would be passionate doing.
Wednesday, May 13, 2009
Friday, May 08, 2009
- Mentor will buy LogicVision, which adds complementary technology to further strengthen their DFT portfolio.
- And, Synopsys will add to their Analog IP offering by buying MIP's Analog business.
Thursday, May 07, 2009
The crises are piling up — software and concurrency, analog/RF, die-package-board and die stacking — and with a fixed number of EDA R&D engineers, we need to stop working on some issues. In the big picture, who wins a power format or current-source model or process variation model war is less critical to semiconductor industry health than consensus, interoperability, and moving on to fundamental design technology challenges.
This is very consistent with the efforts of companies like TSMC to get the EDA industry working cooperatively to solve more problems and add more value, by reducing overlapping development.
Tuesday, April 28, 2009
- Richard Goering (noted EDA journalist) is back online! He's been covering EDA for a long time and has interesting and credible insights. He's writing a blog for Cadence at Industry Insights.
I went to the TSMC Technology Symposium in San Jose
I've been going for the last few years.
These are great for getting road maps of silicon process and design technologies (TSMC Reference Flow).
I wasn't sure how much information I could share from
the day, but Richard has solved my problem by
writing a comprehensive report
TSMC Views R&D As Ticket Out Of Recession.
One announcement that I'd like to call attention to is TSMC's integrated sign-off flow. I'd like to take a look at it. It's initially created for 65nm sign-off, and sounds like a Reference Flow on steroids. Not only are there "approved" tools, but also recommended scripts (which EDA vendors also provide) and other libraries and technology files -- apparently a complete package. I'm curious to see how it differs from what we currently use. I might learn some new tricks.
Monday, April 27, 2009
I'm seeing more and more about 3D packaging, using emerging technologies such as Through Silicon Vias (TSV). Might this solve some of the thorny integration issues people are expecting? If 3D is a good answer for Logic + Memory, it may also be a good match for CPU + GPU. Already, in the CPU space, we're seeing a fair amount of package-level multicore integration, rather than "natively" putting all the cores on a single die. For example, check out AMD No Longer Feels the Need to Go “Native” .
Monday, April 20, 2009
You heard it here second. Lou Covey blogged in State of the Media: Oracle. Sun. Brilliant. that Oracle's play for Sun is part of a scheme to break into the Hardware or (shudder) EDA industries!
It's a provocative theory, but would leave me very, very surprised if that were Oracle's motivation. Perhaps they could improve the financials of the EDA business, or juice up EDA's database architectures. But more likely, it seems to me is that Oracle is looking for control of software assets like Java and MySQL. The server and chip businesses just seem way beyond Oracle's core competencies. I'd guess those may be spun off or otherwise de-emphasized.
5/7 Larry says they're keeping all the hardware business.
Friday, April 17, 2009
I was heartened to hear the President's recognition of the value of scientists and engineers, and their abilities to contribute to a sound economy:
one of the changes that I would like to see — and I’m going to be talking about this in weeks to come — is once again seeing our best and our brightest commit themselves to making things — engineers, scientists, innovators. For so long, we have placed at the top of our pinnacle folks who can manipulate numbers and engage in complex financial calculations. And that’s good, we need some of that. But you know what we can really use is some more scientists and some more engineers, who are building and making things that we can export to other countries.
(New York Times photo)
Interested in visiting Silicon Valley, or brushing up on your technology industry history? Check out American Journeys - Searching for Silicon Valley; a Place and a State of Mind from the New York Times.
Saturday, April 11, 2009
Wednesday, April 08, 2009
Read more about its history and how it works in Circuit Simulation - Part One - SPICE Turns Thirty-Six. It's a nice article where you will either learn a little circuit theory, or have flashbacks of courses you took a long time ago. I used to be able to do these equations in my sleep. Let's not talk about my "current" capability.
If you'd like to learn more about SPICE, look for the blogger to post more parts in his series. There's also The SPICE Book, authored by one of the SPICE developers.
Tuesday, April 07, 2009
these humble documents shape the Internet’s inner workings and have played a significant role in its success
What history! What an achievment! It represents the best of engineering culture, to have an open dialogue to craft the best solution (brainstormimg + compromise). And, it only leaves me wondering, why can't we have more true collaborative standards in our industry?
Monday, April 06, 2009
I've always been a wannabe hardcore software engineer (it was my emphasis for my M.S.), but in reality, am JAPH.
Nevertheless, I enjoy keeping up with new software development methodologies and languages. As far as fluency, I'm in the age of Java and OOP, but I enjoyed this clear explanation of Why Functional Programming Matters in the "Daily Vim" blog.
Even if you aren't interested in new languages just for the sake of it, this snippet shows why it's relevant to strong emerging trends in CPUs, GPUs, and productive programming paradigms:
At this point, the resounding question in your mind is probably, "why bother?" Well, fortunately there's a very strong reason behind all this shifting of methodology, and that's concurrency.
Wednesday, April 01, 2009
Tuesday, March 24, 2009
Some reactions to her points:
- Synopsys is king of the hill. Yes, obviously.
- Cadence should acquire Magma. I could see this happening. That's the kind of thing Cadence has done in the past, and Magma is getting small.
- Bring back Joe Costello. It would certainly energize the industry, but I doubt he'd want to, or that he could fix things alone.
Tuesday, March 17, 2009
One of the new announcements was a surprise to me: a flow management system called "Lynx". There's no way I can describe it better than harry … the ASIC guy � Synopsys Lynx Design System Debuts at SNUG.
I'm curious to learn more about it -- there's a SNUG session on it tomorrow. I'm a sucker for a pretty GUI, and I love automation. But I wonder how much business opportunity there is for this -- what is the target customer, and what is the value to them? Many large companies may already have something in place. But for a company just starting up a flow, this could be a quick start to "best practices" results.
Just don't call it a Framework!
Monday, March 16, 2009
I've followed Woz's trajectory for a long time. I've seen him speak a couple of times, including as a featured guest at the Synopsys Users Group conference a couple of years ago. As a hardware engineer, you can't help but love Woz. He is truly a gifted designer, and his enthusiasm and passion are clear and sincere.
As Apple co-founder, he's a pretty wealthy guy, which gives him the luxury of pursuing whatever wild idea strikes his fancy. He's had a couple of brushes with pop culture (dating an actress/comedianne), but came out in a big way last week with an appearance on Dancing With the Stars.
You can see his debut here Wow! Woz continues to command my respect as a passionate engineer with absolutely no pretense. I can't help but laugh and wonder if this is the best "15 minutes of fame" moment for an electrical engineer, though. Rolling in on a Segway? Pink Boa? Ah, Woz, you really don't care what others think, do you? I love and respect you for that.
Tonight is his second appearance on DWTS. Hopefully it won't be his last. Check him out. And, in solidarity with our engineering brethren everywhere, give him your support. It would be sweet if some hackers got into the phone system and pumped up the votes for his performance. [the roots of Woz's technology wizardry began with "phreaking" phone systems to get free long-distance phone calls!]
Wednesday, March 04, 2009
At a glance:
SNUG San Jose 2009 March 16 - 18, 2009 Location: Santa Clara Convention Center 5001 Great America Parkway Santa Clara, CA 95054
Here's the schedule. Contact your Synopsys support person or sign up online.
Now, of course, the economy is in worse shape, my company is cost-reducing with a vengence, and IEEE membership is up to $169 (a 20% increase by my calculator). To put it politely, what is the IEEE thinking? It's like some government bureacracy run amok, growing on auto-pilot.
All of the concerns about benefits vs. cost, and the unease of not having a home for ASIC design and EDA, still exist. Now the cost has risen much faster than inflation and money is tighter. Time for us to part ways, until "some sunny day". (cue Vera Lynn/Pink Floyd)
Monday, March 02, 2009
Now, I hear Twitter mentioned on MSNBC every five minutes (weird). And last week, Twitter came to an EDA conference. JL Gray and like-minded attendees "tweeted" their impressions of DVCon in real-time. JL followed up the conference with a recap via that "old-school" platform, blogging: Cool Verification: DVCon 2009 Wrap Up: Attendance.
I followed the DVCon tweet stream from time to time, but I felt you really had to be there. I didn't "get" many of the references, though it sometimes left me wishing for a live webcast to see what the excitement was about. Personally, I think Twitter is too hyped-up. Maybe, when most everyone is carrying a cell phone or MID with low-cost unlimited data access, it will create new ways of interacting and experiencing conferences. But for now, it is something to be figured out by early adopters.
Thursday, February 26, 2009
Peggy said EDA tools are overpriced? Huh! How about giving me a quality product that doesn't crash so often! Makes Microsoft Office look like mission-critical software. [a pet peeve of mine which I hope to expand on in a future post]
Wednesday, February 25, 2009
Monday, February 23, 2009
Friday, February 13, 2009
Thursday, February 12, 2009
Tuesday, February 10, 2009
Dan Lyons, more famously known as Fake Steve Jobs, wrote Growing Rich by Blogging Is a High-Tech Fairy Tale for his "day job" at newsweek.com.
It gives insight and some figures on the financial opportunities for bloggers. To cut to the chase: there's not a lot of opportunity! Certainly that's not why I blog, though it's nice to imagine the claimed average earnings of $5,060 per year.
It also gave me more insight into Dan Lyons, the person. As often happens, I liked the "fantasy person" Fake Steve Jobs better. I was disappointed to read that getting rich was a big reason for his launching the Fake Steve Jobs blog, which I found absolutely hilarious. Mark me naive for wishing he just wanted to share his creative gift with all of us. You do have a humourous gift, Dan. May you find a way to re-launch it and make a good living while you're at it.
Wednesday, February 04, 2009
Tuesday, February 03, 2009
Therefore, I'm highlighting a few useful commands or utility packages that an engineer might use regularly. I plan to follow this up with a post on useful free EDA packages. My "go-to" utilities are
- think of it as "text VNC". lightweight and low bandwith. Hey, most of what we do in VNC is textual anyway, right?
- rock-solid terminal client to access *nix from Windows
- free industrial-strength encryption. Because you'd hate to have your USB drive or notebook PC data fall into the wrong hands.
- *nix command to process a list (e.g., of file names) piped from another command
Wednesday, January 28, 2009
Monday, January 19, 2009
I was at the San Jose Tech Museum of Innovation yesterday to see their US-exclusive Leonardo exhibit. It really drives home what a genius Leonardo da Vinci was. He seemed to know everything knowable as of 1500, and the exhibits make it clear that he was a god of mechanical engineering (among many things).
If he were around today, with what's available with electrical and electronic engineering, imagine what he would have created! Who is the da Vinci of our day?
Besides this featured exhibit, the kids I brought and I explored the other Current Exhibits. I was excited to find displays on semiconductor design and manufacturing in the Silicon Workshop.
The design section is sponsored by Cadence and the EDA Consortium, and has hands-on activities showing what I knew to be logic design and physical design. I was excited to explain to the children how a few simple logic gates could be interconnected to control what actions would start the model car, turn on its lights, etc. And I think they enjoyed it, too.
Ask me again in ten years whether this influenced the kids at all to pursue science or engineering. I think it is a good attempt. Props to Cadence and EDAC for creating this to show what we do and inspire the next generation.
(images linked from The Tech web site)
Friday, January 16, 2009
has variously been reported as "just a layoff", or, in this headline, layoffs + executive salary cuts. But if you read the article, the salary cuts apply to everyone who survives the layoff. Exempt employees, which includes engineers and other professionals, will get a 10% pay cut.
Ouch! People would prefer a cut to being laid off, but 10% could be quite a challenge for those who've been good consumers and not such good savers. I'm concerned that these measures will become more common as the economy continues to struggle.
As an aside, the article curiously mentions voluntary pay reduction measures for employees outside North America. What's a "voluntary pay reduction"? Does it mean "sacrifice for the greater good", or "volunteer or else something worse might befall you"?
Wednesday, January 07, 2009
Maybe rather than yet another blog post of 2008 review and 2009 predictions, I'll just flag provocative ones like EETimes.com's Top 20 predictions for semis in 2009 by Mark LaPedus.
Some of my favorite points:
That's a lot of quoting, but there's even more good stuff in the article. The author definitely "names names" of which companies may fail and which will prevail.