DAC Appeals to Users

When I first started attending DAC (1990 in Orlando), as an ASIC designer who'd recently joined an EDA group, I found it disorienting. The exhibits floor seemed like a circus with attendees rushing from one booth to the next to collect the best schwag (some things never change). I dutifully sat in paper presentations that sounded interesting, but I soon realized they weren't addressed to designers or users. I came to think of them as "PhD theses showing a routing algorithm that performed 13% better on an academic benchmark". Not to belittle those papers -- the mathematics and rigor impresses me greatly, but I don't understand all of it or apply it in my job.

Over the years, DAC has become more user friendly. The panels in particular are often informative and sometimes provocative. I find that I'm getting more and more out of DAC.

This year, there's an explicit "User Track" at the conference. I'd like to share a description of the User Track while presenting the first guest post on John's Semi-Blog. Please enjoy!

User Track at DAC:  Learn from Your Peers

Soha Hassoun
Tufts University
46th DAC Design Community Chair

Leon Stok
IBM
46th DAC New Initiatives Chair

Today’s connected world makes it possible for you to work from everywhere.  Yet, there’s only one place where you can learn how your peers successfully applied design tools to chip design and where you can exchange valuable experiences:  the new User Track at this year’s DAC.

The three-day User Track features 40 presentations that run in parallel with regular technical sessions.  Speakers include expert designers from Cisco, ClueLogic, Fujitsu, IBM, Infineon, Intel, Qualcomm, Samsung, STMicroelectronics, Sun, Texas Instruments, Virtutech, Xilinx and others.

Identifying Front-End Challenges

Power planning and verification continues to be hot.  A team from NEC will detail an automated flow to pre-characterize the power consumption of a set of basic components starting from their behavioral description in C, down to their power estimation at the gate-level netlist.  A team from Cisco will describe the use of a power noise analysis tool to analyze system power integrity.  Engineers from Texas Instruments will illustrate how they used an EDA tool to integrate complex multi-power/voltage domain design.  Intel engineers will present a flexible, high-level power management modeling and simulation framework for power architects.  And, a team from STMicroelectronics and ST-Ericsson will outline an exploratory and refinement-based power planning system.  Also, Intel engineers from India and Israel will offer a novel direction for using abstract executable models to verify power management protocols.

Tackling Backend Challenges:

In the Practical Physical Design session, a team from Intel will discuss how they tackle ECOs as late logic changes delay the process and register arrays occupy more than half of all transistors of modern designs.  Qualcomm designers will describe how they build their semi-custom methodology and STMicroelectronics engineers will outline e how they use the IP-XACT standard from Spirit to enable IP reuse.

Accurate power supply and substrate noise analysis remains a challenge, and practitioners from Qualcomm, IBM, Samsung and Kobe University will show how they attack the problem.  Texas Instrument designers will show how to analyze blocks for reuse in multiple metal stacks.  Intel engineers will highlight their approach to assessing design feasibility early in the process to avoid problems later.

A team from Stanford University, Rambus and Netlogic describes a way to tackle analog reuse as it becomes as important as reuse is in digital design.  A group from Cadence and several Taiwanese universities will describe their approach to integrate MEMs in mixed-signal designs.  Engineers from NXP and Magwel tackled the problem of analyzing substrate noise and will present their results in 90nm process technology.  With complex circuits often needing an integrated approach to physical and electrical verification, a team from SysDsoft and Mentor describes how they accomplished this on their designs.

In addition, join us for an Ice Cream Social Wednesday from 1:30pm-3pm where 42 posters will offer an opportunity for you to mingle with other EDA tool users. 

Access to the User Track is included with the full-conference registration.  Or, register separately for the User Track and get access to the keynotes, in addition to the User Track.  For more details, visit:  www.dac.com.  We look forward to seeing you in San Francisco.

###

For more information:

Nanette Collins

Publicity Chair, 46th DAC

(617) 437-1822

nanette@nvc.com