Friday, August 07, 2009

Found at DAC

My pre-DAC post Looking Forward to DAC laid out what I hoped to investigate by visiting exhibitors, namely

  • Low Power
  • Datapath
  • MCMM
  • parallelism
  • Asynchronous Design

Well, despite my best-laid plans, I wasn't able to check all these items on my list in two days of roaming the exhibits floor. In some cases (i.e., Asynchronous Design), I didn't find an appropriate vendor. In other cases, my schedule or the vendor's appointment constraints didn't allow me to gather the information. But DAC was a great opportunity to see many vendors, and by careful plan or happy accident, I was able to visit many interesting companies. I'll group my vendor impressions into these categories:

High-Performance Design

  • It seemed like Oasys Design Systems was the most talked-about implementation vendor at the show. As I've said before, their capacity and run time claims are incredible. At this show, they put a lot of emphasis on making their claims credible. They've got some customer testimonials to validate them, and their closed-door demo suite explains what's revolutionary about their physical synthesis approach, and why it could be dramatically faster than today's synthesis tools. Update: Harry the ASIC Guy explains technical details of Oasys' approach.

    And to top it all off, I just about ran into Joe Costello on the DAC floor. (He was suspiciously near the Synopsys booth at the time.) It should be great to have Joe back in the EDA industry. I like and respect Aart de Geus a great deal, but Joe Costello can add motivation and excitement back to an industry that's feeling tired.

  • Micro Magic is an interesting small design/tools company that's been around almost 15 years. Because DAC wasn't very crowded on Wednesday, I could walk into their booth and have a long informal chat with their CEO. He exudes confidence and credibility.

    One of their tools is a Datapath Compiler, which is one of the few commercial solutions for maximum performance datapath design. Other companies have come and gone (Arcadia is long gone; Arithmatica wasn't at DAC), but Micro Magic apparently has numerous real success stories. (Their customers seldom allow themselves to be named.)

  • iNoCs is an early stage startup with tools to synthesize Network on Chip (NoC) IP. Their debut was especially timely because NoC was one of the technologies featured in the Wednesday Keynote by Bill Dally, Stanford professor and NVIDIA Chief Scientist. As it turns out, the connection is even stronger. iNoCs is advised by noted EDA professor Giovanni De Micheli, who has been a colleague of Professor Dally.


  • The only company I met with a heavy focus on new parallel computing products was ACCIT, which is developing highly accelerated SPICE simulators running on ATI GPUs. Looking forward to the NVIDIA CUDA port, guys!
  • Of course, many of the big EDA vendors are adapting their products for multi-core technology, for example Synopsys PrimeTime Multicore.

ESL Synthesis

I spoke to a few vendors in this space, but I wouldn't dare pretend to have a good grasp on where the field is at. Several journalists and bloggers are writing "now is the time for ESL synthesis", but I have yet to meet the designers using it or even enthusiastic to get into it. It's puzzling to me. There apparently are specific domains with considerable success, such as wireless and image or video processing. And there are specific geographic areas adopting it first, namely Japan. But for the mainstream ASIC designer, I don't yet see it catching on.


I liked what I heard in a brief visit with Imera, which develops hardware+software solutions to allow secure remote debug of software (e.g. EDA tools). In my work, there is constant antagonism between the EDA vendor, whose engineers claims they cannot debug their software beyond their walls versus the EDA customer, which doesn't want the "company jewels" of full-chip RTL or netlists to ftp over to the EDA vendor. Imera has solved the problem with a distributed debugger and networking solution that allows the R&D engineer to debug from the vendor side, while the EDA tool is running on the design data at the customer's site. Sounds like it would resolve the stalemate and allow us to get on with the problem-solving.

Overall Impressions

I had not attended DAC since 2006. It was a little disorienting because of all the changes in the industry and the conference itself. Attendance was way down from boom times. For the first time, I had an "exhibits only" pass, which allowed me to go up every day and visit the exhibits floor but not the technical program. After Free Monday, the floor was much less crowded, and it was a pleasure to walk right up to any vendor and get all my questions answered. One irritating practice of several vendors was to not have any open demos, but to require a one-hour appointment to be scheduled for a closed-door meeting. I found this quite inconvenient for any sort of spontaneous discovery, and as a result both vendors and I missed out on some worthwhile discussions.

I was glad I attended DAC. I obtained information that will help me in my job, and met old and new friends. I wish for the sake of the organizers and the exhibitors that attendance had been stronger, but the economy was a strong tide to fight. Let's hope that tide is turning and the 47th DAC in Anaheim will celebrate a growing vital EDA industry.


George Harper said...


As you're aware, I'm particularly interested in ESL Synthesis (for everyone else, and for full disclosure, I'm with Bluespec).

There's been a distinct increase in discussion and hype around ESL Synthesis in the last year. And, no doubt, behavioral synthesis tools have gotten a lot better than they were 10 years ago. But, they'll never overcome the fundamental limitations of sequential languages.

So, I share your skepticism about the "mainstream ASIC designer" adopting the C/C++/SystemC synthesis tools. Good hardware design fundamentally requires explicit parallel programming -- and, of the three, only SystemC provides that, but does so at a low-level of abstraction. And, from what we've seen, even in the 'datapath' or 'algorithmic' domain, sequential languages are often not the best source for an optimal hardware design (and there's no way to tell this a priori).

Until ASIC designers are willing to make significant compromises in area, throughput, latency, or some other QoR dimension, I don't believe there will be mainstream adoption of the C/C++/SystemC-based approaches.

NVidia's Bill Dally had a great DAC keynote on Denial Architecture (everyone should see it): that is, being in denial about parallelism and locality. This argument is equally applicable to those depending on automatic parallelism technologies, which are fundamental to the value of C/C++/SystemC-based synthesis. (If overcoming these fundamental considerations was imminent, there would be no “parallel software crisis” today for programming multi-threaded, multi-core and GPGPU machines. Both behavioral synthesis and "paralleling software" require the same CDFG analysis.).

Mainstream adoption requires time -- but it also requires solutions that don't compromise designer transparency and control while also providing a useful/valuable new level of abstraction.

This is something that an explicitly parallel approach like Bluespec can offer.

- George

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