Anticipating DAC

The Design Automation Conference is coming up at the end of July in San Francisco. Expect the Silicon Valley crowd to be out in force.

There's been some griping that there's no "Free Monday" this year. Instead, there's an all-days Exhibits Pass available for $50. To me, that seems like a very reasonable proposition. It remains to be seen if this will cause a significant drop in attendance, and if those who won't pay $50 are the ones EDA vendors need to see at their booths.

As the conference approaches, there will be a number of "must-see" lists, and I hope to compile my own. Right now, I don't have a very clear idea about companies to see. I do have some ideas about what may be hot, from my ASIC design implementation-centric point of view.

What Should Be Hot

• Multi-threaded & Multi-core software. Initially, these trails were blazed by startups such as Extreme DA and Sierra Design Automation (now part of Mentor Graphics). Now, all the major EDA vendors are working hard at either developing new products or retrofitting established ones. Richard Goering has had a number of interesting technical posts about how it's going at Cadence.
• Multi-Corner Multi-Mode (MCMM) analysis and optimization. This has also been talked about for a long time. It's always seemed like a good idea, but is becoming more critical at the most advanced processes and design sizes. A key question is how practical this is. What is the performance penalty to go to MCMM? Helping to solve this will be multi-threaded & multi-core software.
• Low Power. Of all the "next big thing" areas of EDA, this has struck me as the most real. There are several viable verification products based on simulation or static analysis. For implementation, there's combinational and sequential clock gating, multi-Vth optimization, and support for voltage and power domain design driven by UPF (or in Cadence's case, CPF ;-)

Ready for Prime-Time?

• I've been doing a lot of reading about variation, and various techniques to account for this. It's a fascinating new way to think about semiconductor performance. But, there is so much that needs to fall into place for statistical techniques to be used in production: tools, libraries, and a new way of thinking about design analysis.

Count Me Skeptical

• ESL. Maybe it's the market I'm involved in, where "QoR", especially performance, trump potential productivity gains at higher-abstraction design levels. This may be more attractive when time to market is everything and the QoR tradeoff not so great.
• RTL analysis & design planning. Again, maybe it's because of where I sit, but you can argue about getting too carried away with analysis at RTL. RTL is the functional description of the design. Implementation can be done "downstream" of that.

So there's a stake in the ground. I'd love to hear your comments on what the hot trends and companies will be in EDA this year. Hope to see you at DAC!