I agree that SystemVerilog looks to be a better way to design and verify. It's more productive, removes some Verilog ambiguity, and has better support for formal verification.
I don't know the prospects for OpenAccess (hope it's not another CAD Framework Initiative or CHDSTD), but hope it succeeds. As Richard says, why should every startup (and every corporate CAD department) have to redevelop the infrastructure for EDA tools?
Don't know much about SystemC. Let's start using SystemVerilog first.
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The fight between SystemVerilog and SystemC has never been fought on technical merits or demerits, but rather on marketing turfs.
Check out this article by Gabe - http://www.edn.com/article/CA417185.html
Till now, ESL has never gained a lot of industry acceptance (going from systemC to tapeout for example), but I think introduction of tools from Calypto, etc. will ease this transition.
OpenAccess is a completely different story. It is meant to be a database format used by EDA development teams. I think its pretty cool. This way we can focus on functionality algorithms rather than housekeeping tasks (like saving snapshots to disk, accessing design models at high speed, etc.)
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