I agree that SystemVerilog looks to be a better way to design and verify. It's more productive, removes some Verilog ambiguity, and has better support for formal verification.
I don't know the prospects for OpenAccess (hope it's not another CAD Framework Initiative or CHDSTD), but hope it succeeds. As Richard says, why should every startup (and every corporate CAD department) have to redevelop the infrastructure for EDA tools?
Don't know much about SystemC. Let's start using SystemVerilog first.