Wednesday, February 06, 2008

ULTRA Low-Voltage Design Reported

Energy-efficient Microchip Could Result In Cell Phones Staying Charged 10 Times As Long, Self-charging Electronics describes a design done by MIT and TI researchers showing operation at 0.3 volts. It includes several interesting features, such as
  • On-chip DC converter to reduce voltage
  • Designed to minimize manufacturing variation
  • 0.3 volt operation at Idle mode, which implies Dynamic Voltage Scaling (DVS).
  • Memory uses an eight-transistor bit cell, which improves retention at low voltage.
Lowering voltage is actually the standard for lowering system power," said Dean McCarron [President of Mercury Research]. "The challenge is that when voltage gets to a certain level, generally around 0.8 to 0.9 volts, making the chip work becomes more difficult. You know, 0.9 was thought to be the floor, and these guys have broken through the floor.

The researchers are describing their work in a paper presented at the International Solid State Circuits Conference in San Francisco. See also this Computerworld article.

1 comment:

Sandeep said...

Very nice find John!!

Especially this part:

"Designing the chip to minimize its vulnerability to such variations is a big part of our strategy," Chandrakasan says

New EDA tool??