Tuesday, July 25, 2006

DAC is Here!

EE Times is doing a nice job of covering the Design Automation Conference, which started yesterday in San Francisco. Road to DAC: Complete Conference Coverage has lots of articles and even a set of webcasts that includes an interview with Joe Costello, former Cadence CEO and EDA celebrity.

Thought I'd post the list of companies that I'm interested to visit. It is far from a comprehensive list, but these are companies mostly in the "design implementation" space that piqued my interest based on what I've read.

  • Altos - Statistical timing characterization
  • Apache - IR drop analysis.
  • Athena - simultaneous timing closure (post-route)
  • Azuro - low power clock implementation
  • ChipVision - Low-power ESL design
  • Extreme DA - Statistical STA
  • Forte - SystemC synthesis
  • Magma - Talus implementation system, Blast Fusion design closure
  • Proficient - Low power design
  • Prolific - post P&R timing optimization
  • Sierra DA - physical synthesis & routing.
  • TSMC - Reference Flow 7.0
  • Zenasis - custom cell generation for timing optimization

1 comment:

Simon Kinahan said...

Did you make it to the Azuro stand? I was demoing there this year. We had an excellent DAC. Hope you did too.