One thing I'd wonder about is how design teams can accurately convey their timing environment to TSMC (across all modes and corners) such that these optimizations don't break timing. Running sign-off STA is not quite as simple as "just send an SDC file over". :-)
Friday, April 18, 2008
DFM heads into the foundry
And we're back to the "Hacking Cough" blog for this analysis of
DFM heads into the foundry.
The post explains an innovative announcement from TSMC whereby they will offer
as a service
Blaze DFM's power & variation optimization capability.
The innovative part is that instead of a chip design company buying
the EDA tool, you pay for it as a service from your foundry (exclusively
TSMC at this time).
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3 comments:
Hi John,
I would guess that the Variation in Leff by the fab would still fall under the OCV umbrella which the design teams have used during the design phase and still bring about that 10% leakage reduction :).
Hence it would still not break the timing.
with More technologies like this entering the main stream, very soon people are going to adopt SSTA.
If you go to the Blaze Website there is a description of the process they use:
1) Performs STA on final GDSII and outputs information forward to OPC tool. It seems this analysis identifies paths with positive slack for hold and setup.
2) OPC uses this info to help it make OPC decisions that favor lower leakage, e.g. increase gate size to raise Vt on paths with timing slack. Changes are < 3nm.
3) The also claim it can improve timing margin by varying gate lengths to slow down paths with tight hold time margin and speed up paths with low setup margin.
In essence, it's kind of like multi-Vt on a cell by cell basis.
I recall some years ago that a consulting services client of Synopsys was doing something similar in the transistor world, not in OPC, scaling transistors along the critical paths. In essence they effectively had an infinite set of Vt cells.
This sounds very cool. And I agree that the business model makes a lot of sense as well. Best thing is that they don't have to knock on the doors of every fabless company.
Hi Harry,
Great stuff.
So Blaze is signoff according to TSMC for timing? Incremental timing?
Or do they can feed in PT and PT-SI reports into their OPC tool to do this stuff?
Since a large change in gate length would effect cell timing in a big way and would warrant timing closure iterations, I was of the opinion that they were going to tweak the cells in a very incremental manner and get those leakage improvements.
Hence I was of the opinion that these incremental changes would be as good an OCV based analysis in a current timing signoff scenario.
Is there another timing signoff iteration needed post Blaze DFM tweaks? If not, thats wonderful news and Blaze not only as a DFM engine which can give those leakage imporvements, but also has a signoff timer.
-Nick
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