"Hi, I'm a RealTime Designer. And I'm a DC."

Look what one can miss by not attending DAC! I didn't realize that Oasys put together a bunch of videos poking fun at Synopsys (and ripping off Apple's commercials). See Oasys' DAC videos. I would have liked some more inside jokes about the competition's shortcomings, but we get the general idea.

As a bonus, the well-produced DAC 2009 video features company executives in a music video with cheesy parodies of some classic rock songs. I'm amused, but Al Yankovic need not worry.

Props to DeepChip.com for leading to my discovery of these gems.

What's inside Verizon’s Apple iPhone?

Verizon's version of the iPhone is just out and a couple of "teardown" companies have already sacrificed samples to see what's inside. Steve Leibson has their parts lists at Teardown of Verizon’s Apple iPhone reveals chips used. Want to know how many and which ones? Want to see the video teardown? | EDA360 Insider.

Most Dominant Franchise in EDA

I got to wondering -- which tool has the biggest lock on a major piece of the EDA tool constellation? (I originally wrote "monopoly" instead of "franchise", but don't want to connote market manipulation.) From my perspective, three come quickly to mind

• Cadence Virtuoso
• Synopsys Design Compiler
• Synopsys PrimeTime

You may have other ideas, and I'd love to hear other nominations. Of these three, I think a good case can be made for Design Compiler having the strongest position. The other tools have large market shares, but also competition determined to make inroads.

Who might chip away at the synthesis gorilla? The old and new rivals are Cadence RTL Compiler and Oasys Real Time Designer. Just published on ESNUG is this "marketmonial" (I need a word for a marketing-inspired testimonial): DeepChip.com: "An Oasys RealTime Designer vs. SNPS DC-Topo/DC-Graphical benchmark . A couple of things that I especially like about Oasys' approach:

• If Oasys truly optimizes at a higher level of abstraction (physical feedback can change the way RTL structure is synthesized), then substantial performance advantage claims become believable
• It freely exports DEF and integrates with the physical design world. By contrast, DC Topographical/Graphical can't decide whether it wants to be complete physical synthesis or "PD-lite", not fully supporting or integrating with detailed physical design data. (RTL Compiler is open like the Oasys tool in this regard -- it interfaces with Encounter P&R tools using standard data exchange formats.)

Time will render the verdict, and the EDA battlefield is littered with past attacks on DC's franchise, but we need competition in all tool areas to continue advancing the state of the art.

Oops!... Intel Did It Again

Intel, if you need reliable designs to support your latest CPUs, there used to be a variety of companies in the chipset business.

January 2011 had more than its fair share of bad news for Intel, culminating in a very expensive recall of their newest chipsets because of a design defect. Most of the press coverage focused on the financial hit, but us design engineers are dying to know "what happened?". What's most interesting is that the problem isn't a defect that manifests itself right away, but one the causes the component to deteriorate over time. At first, I thought "electromigration". But the best speculation/analysis I've seen this early has been from Mike Demler, who shares his theories in Price for a new SATA I/O $700M. A complete AMS verification? Priceless! and If ever EDA needed a ($700M) proof point on their value....

If that's the root cause of this problem, it's another data point showing fraying at the edges of our tried and true EDA suites: tools are not available or mature to help with analyzing reliability, materials, packaging, etc.

Update: Thanks to a link from Steve Leibson, I came across this very specific description and analysis of the problem.

Birth of a World Beater

If you followed the Consumer Electronics Show news at all last week, you heard a lot about ARM, ARM, ARM. Mindshare-wise, it would appear to have Intel on the defensive. (I wonder how Intel feels about selling off their StrongARM now?)

I plan to learn more about ARM's architecture and products. For today's history lesson, Birth of a world beater features one of the original ARM designers.

I'm curious to learn the technical merits of the ARM architecture. Is it inherently superior? Or is the main advantage the scads of software eco-system available, with low-power coming from standard implementation and process tricks?

Technical superiority and business success don't always go hand-in-hand, anyway. I've attend HOTChips before, and I was amused how all the microprocessor experts there bemoaned x86's incredible success, even though they knew it was inferior to [insert your favorite CPU here];. x86 was just good enough to survive, and had been in the right place at the right time. Is now the time for ARM?

Fancy Video of a Modern Fab

Here's a cool video to give your family and friends an idea of what our industry produces: Thanks to sleibson for his post Watch Lexar make them memory chips – Months of time compressed into six minutes of video | EDA360 Insider.

Early in my career, I got to visit the IBM Burlington fab when they were introducing a brand-spanking-new technology called "CMOS". Little did I know that would be my last chance to set foot in a semiconductor fab. So, I'm always fascinated to see how things look today. Some things I learned:

• there's another domestic fab besides Intel and IBM!
• Micron owns Lexar?
• some of the coolest automation is the mechanical stuff, like the wire bonder and the laser marking

First There Was Semi-Blog

now: SemiWiki! Created by several fellow EDA bloggers, this is an intriguing new EDA/Chip Design site worth visiting and contributing to.

I know that several bloggers and old ASIC hands wanted to put together an open community for sharing opinions and experiences, and this is the most substantive effort to date. (I tip my hat to John Ford's now-defunct "DFT Digest" site, which was a pioneer in this area.)

The Next Big Thing is Cloudy

sorry, I couldn't help sharing--

Sadistic HR Department?

I couldn't resist reading an article titled Apple's HR Department Is Obviously Filled With A Bunch Of Sadists!

Could you figure out the answer? To my frustration, I couldn't, without peeking at a few of the comments. It makes perfect sense now. Not a bad puzzle!

Headhunter in a Nutshell

If one of your New Year's resolution is to look for a new job, here's a holiday gift: some provocative, sensible advice from Ask The Headhunter® | Nick Corcodilos – Ask The Headhunter in a Nutshell.

I've read Nick's newsletter for a long time and recommended it, his web site, and his book to many people. What I like is that much of it is more sensible and less trite than so many of the job-seeking rules of thumb that you read. I don't agree with him 100%, and some of his advice seems hard to implement, such as refusing to disclose your current salary. But, he has good reasons and it's all worthy of your consideration.

I hope you are enjoying the holiday season and wish you interesting projects and prosperity in 2011!

A Concise Story of the ASIC/EDA Business

Check out Jim Hogan's article, The evolution of design methodology.

Past history is crystal clear and his description spot on. His assessment of current and future value-add is plausible and thought provoking. Sounds dire for many silicon-centric companies, though. Will you be a survivor? What does it say for the fortunes of the EDA industry? His answer seems to be focus on system/software, complemented by C-based hardware design.

Magma & Synopsys CEOs Discuss Quarterly Results

It's been a good year for EDA stocks. Here are the latest CEO business discussions from Synopsys and Magma:

• Synopsys CEO Discusses F4Q2010 Results – Earnings Call Transcript -- Seeking Alpha
• Magma Design Automation CEO Discusses F2Q2011 Results – Earnings Call Transcript

To 22nm and Beyond!

I wish I had gone to the ARM Technology Conference. Lots of good design topics, and some long-range prognostication such as IBM Speaker Outlines Path to 22nm and Beyond. This blog post by Richard Goering of Cadence summarizes a talk by a VP of IBM's semiconductor research center. For 22nm, they main change appears to be more "lithography tricks". Richard includes a link about "double patterning".

Beyond 22nm, many things get exotic. Extreme UV (EUV) has been the next big lithography change for ages -- is it finally required for 15nm? FINFETS, Carbon Nanotubes, and Stacked Die, Oh My! We're not in Kansas any more.

LSI Logic's 30th reunion!

Who's who at LSI Logic's 30th reunion gives a great synopsis of the pioneering company in the ASIC/EDA industry. To read the whole story, track down a copy of Silicon Destiny: The Story of Application Specific Integrated Circuits and Lsi Logic Corporation, by Rob Walker, one of the founders of LSI Logic. (I have an autographed edition!)

Intel Opens the Factory Door. A Little.

In the early 2000s, Intel dabbled in becoming an ASIC vendor. They eventually cancelled that business venture. Now we read that Intel, in a very controlled way, will be Making Advanced Chips for Third Parties. Advanced, as in 22nm!

But this is much more focused than a merchant ASIC business. FPGA itself is more like a Standard Product, with high volumes and lots of benefit from using advanced processes. Altera and Xilinx are the most leading-edge customers for the established foundries. It'll be interesting to see Intel's motives beyond just "further monetizing the fab".

There's a New Supercomputer in Town

Well, not in my town, but China has made a great leap forward to nab the lead in the Top 500 Supercomputer list, as described in NVIDIA Tesla GPUs Power World's Fastest Supercomputer

It's exciting to see GPU Computing gaining traction and accolades for certain highly parallel applications. I'm anxiously looking forward to GPU Computing helping to solve EDA problems. So far, there's been some nibbling around the edges and algorithms experimented with, but I'm not aware of production EDA products based on GPU. Yet. What EDA applications would most benefit from massively parallel processing, such as is offered by a GPU?

Blue Light Special on Software

Software is on sale in China! So says Software Companies Lower Prices to Fight Piracy in China, which reports that Microsoft and Autodesk are slashing prices of their OS and CAD software, respectively, in an effort to capture some revenue for their otherwise widely-pirated software.

Does the same thing happen with EDA software? The state of the EDA business in Asia is something I only know from the occasional rumor. How widespread is EDA piracy? How common is it to "crack" FlexLM? And, is EDA software already heavily discounted in Asian markets?

The last point most concerns American workers. Not only are American competing from a higher wage/cost-of-living, but what if the essential tools of our trade are cheaper overseas, as well? Strike two!

Insanely Great Principles

With Apple firing on all cylinders: taking over the mobile electronics market, increasing computer share, and, by the way, attaining the second largest market capitalization in the world, it's instructive to reflect on characteristics that make Steve Jobs such an effective CEO, as described in John Sculley: The Secrets of Steve Jobs’ Success [Exclusive Interview] | Cult of Mac.

Though I'm not sure I'd always like to be his employee, it is pleasing to be his customer. Customers willing to pay a stiff premium are the sincerest form of flattery.

SNUG San Jose 2011 CFP

The Call for Papers is OPEN for SNUG San Jose! Deadline to submit is November 5, 2010.

As my readers know, I find SNUG to be the most valuable conference for hands-on IC design engineers. I always leave with a list of new ideas to try back at work.

Why not launch your publishing career and boost your reputation by showing the cool stuff you've worked on?

Collusion Happens

Synopsys F3Q2010 Earnings & Focus

I don't read all the EDA companies' investor reports and analysis, but the transcript of Synopsys CEO Discusses F3Q2010 Results - Earnings Call gives you a concise view of Synopsys' recent successes and future emphases.

Top themes:

• IP. The DesignWare team is chugging along with significant and growing business, augmented by the Virage Logic acquisition.
• Systems
• FPGA Prototyping

Product-wise, Aart emphasized their custom design competitor to Virtuoso, which I don't find super exciting. It's always nice to have a more modern implementation of a workhorse tool, but not earth shattering. Synopsys bread and butter tools, which pay the paychecks, didn't get much air time.

I think some of the market share claims could be misinterpreted (90% of 32 nanometer chips), but that's standard fare for the ways vendors advertise this.

Rethinking Digital Design

Famed Stanford professor Mark Horowitz is giving talks on Why Design Must Change: Rethinking Digital Design. The questions raise provide refreshing distraction from the day-to-day concerns about the economy, lack of growth in EDA, and creative destruction in the semiconductor industry.

Prof. Horowitz's solution is provocative and plausible, though not a "slam dunk". I'd like him to quantify how much his approach would reduce the total cost of nanometer semiconductor design. Also, how applicable is it to domains beyond processors? Isn't it very difficult to create an "architecture generator" for each domain? For another perspective, here's a blog post reviewing the talk.

Best Companies To Work For

The 25 Best Tech Companies To Work For uses data from Glassdoor.com to aggregate the anonymous, inside scoop on what's good and what's not at employers.

Companies on the list relevant to EDA/ASIC engineers:

• #1 Google
• #4 Apple
• #7 Qualcomm
• #12 Juniper
• #14 MathWorks
• #15 Analog Devices
• #17 Intel
• #22 Synopsys "employees love their CEO"
• #24 Cisco Systems
• #25 Texas Instruments

Moore's Law for EDA?

Thank you, EDA vendors! From Semiconductor input costs vs output prices -- managing the squeeze:

SURPRISE: EDA cost per transistor is coming down the same learning curve as all the other input costs like materials, chemicals, labor, etc. (above) and it has been doing so throughout semiconductor history.

What is Wally Rhines' prescription for increased EDA value-add (and profits)? EDA vendors

... must incorporate the embedded software development and system analysis costs into their design tools and flows. To the extent this is accomplished, there isn’t a cost problem and the 30%+ per year per transistor cost reduction can be achieved. That’s why EDA companies first became involved in embedded software in the mid 1990’s. That involvement will grow as EDA companies take on more responsibility for the total design challenge and its costs. It’s just part of the evolution of roles in the semiconductor industry. (Walden C. Rhines is chairman & CEO, Mentor Graphics Corporation.)

Although in the short term there are still plenty of us fighting it out for nanometer-scale timing (and now power) closure, the focus on software and systems is plausible for the long term. We must find quantum leaps in productivity to take advantage of Moore's law in semiconductors.

SKMurphy's DAC 2010 Meta-Post

Sean Murphy has done a great service in compiling much of the Design Automation Conference coverage in his DAC 2010 Blog Coverage Roundup. It merits close review, and is an especially welcome resource for people like me who weren't able to attend the show.

You can see other trip reports and interesting links in the delicious.com sidebar of my blog, where I post EDA and Semiconductor links.

Spying DAC from Afar

Vendors to See, Vendors to Overlook?

I don't mean to become a "riff on John Cooley" blog, but it turns out he's pumped out some provocative missives leading up to next week's Design Automation Conference (DAC). I was about to write a post on "what I'd see at DAC", when along came Cooley's Cheesy Must See List for DAC 2010. Before we review his list, let me offer my own list of interesting products and technologies. This won't be as expansive as John's list, since I spend most of my time using or considering implementation tools.

Intriguing Products

• Magma Tekton. The tool is targeted to be a better, more modern PrimeTime. Usable as a drop-in replacement, with claimed significant speed and capacity advantages, and attractive added features like SPICE integration and MCMM analysis.
• Oasys RealTime Designer. I wrote about Oasys last year, when they came out of stealth mode. Now, they're rolling out customer testimonials from Xilinx and Juniper Networks. Harry the ASIC Guy, who's been around the EDA industry, has some interesting theories about where Oasys may find business.

Interesting Technologies

• Silicon IP. This is the most sure-fire way to develop 45nm and 28nm chips in an economical way. But do you want to become the general contractor for a dozen IP vendors? You may not have to, with consolidation such as Cadence acquiring Denali and Synopsys acquiring Virage Logic.
• ESL. It's always seemed like a logical step up the abstraction ladder to rise above RTL. There's lots of M&A activity here, with Synopsys and others gobbling up ESL synthesis companies.
• Variation-Aware Analysis. Will SSTA ever be ready for prime time? It's been the Next Big Thing in EDA for a few years, but there is little PT-VX talk at SNUG, and most of the STA startups are focusing on beating PrimeTime at traditional corner analysis rather than SSTA.
• Asynchronous Design. I'm intrigued by not having to synchronize a clock across a chip, and hardening cross-chip interfaces to variation. But I've seen little in the way of IP or automation to realize such unconventional design techniques. Are there any vendors out there? Who are the academic research leaders?

The Cheesy List

I do admire John Cooley's list for its breadth. For the most part, I think he hits the major players in each area and captures the talking points that they're featuring for this DAC.

With one notable exception. Did you notice that his list doesn't feature a certain EDA company that's hard to overlook? That's right, Synopsys. He doesn't feature one Synopsys product in his list! That's a curious oversight to me. While I do think that much of EDA innovation comes from smaller companies, Synopsys does hold its own in innovation compared to Cadence or Mentor, but those companies did have featured products in John's list. Are John and Synopsys having a spat, or is he getting ready to roll out his exclusive must-see Synopsys list?

Pre-DAC EDA Gossip and "User Evaluations"

John Cooley is the original user's voice in EDA, and his DeepChip web site and mailing list continue to have the biggest following. I used to think of John as "the Michael Moore of EDA" -- a rabble-rouser, confronting the dominant companies and their executives, and sticking up for the little guy.

He still has that image, but I've come to realize that the in-depth tool evaluations that he posts aren't always the innocent sharings of chip engineers that they appear to be. There's definitely an element of the EDA vendors' PR machines in some write-ups. That's OK, as long as you take them as such. If these articles are really EDA vendor white papers or press releases, at least they're written in a language that speaks directly to the challenges we face in chip design. With that caveat, here's a list of his latest nuggets:

• Rumors on Synfora, Forte, CatapultC, AutoESL, CoWare, Calypto, EVE. This doesn't read like EDA vendor spin, but rather some provocative EDA-insider scoop on M&A in the ESL space.
• A follow up first evaluation of Atoptech's new Apogee floorplanner
• Another production user on NextOp's BugScope assertion synthesis
• Some hands-on user experiences with HLS and AutoESL's AutoPilot
• Getting 100X scan compression with Talus Design and Mentor Tessent
• Cadence Virtuoso and Solido for variation-aware custom design. (clearly labeled as a white paper)
• Whitepaper on IC Manage unifying bug tracking & design management. (clearly labeled as a white paper)

2010 IEEE Medal of Honor Winner: Andrew J. Viterbi

Interesting profile of one of the giants of modern day technology, who's contributions we use and design with every day: IEEE Spectrum: 2010 Medal of Honor Winner: Andrew J. Viterbi.

At What Price Growth?

The blogosphere is afire with commentary on Cadence's acquisition of Denali, including

• Cadence to Acquire Denali: The Facts | Gabe on EDA
• Cadence to Acquire Denali: The Analysis | Gabe on EDA
• Cadence tries to avoid the Tality trap | Chris Edwards

Though I'm not a financial analyst, I do have reasonable familiarity with the stock market. And, being the thrifty guy that I am, I'm having trouble to justify Cadence's valuation of Denali. Pulling a quote from Gabe's analysis post, Denali had trailing twelve-month revenues of $43 million, implying a 6.3x EV/sales. Priced at over 6X Sales! For a company that's been around a number of years, and while it has a healthy business, is not forecast for hyper-growth? How do companies justify such valuations? (I'm asking sincerely--perhaps there's an analysis angle that makes this look like a good bet.)

The more I read, the more I scratch my head about whether this is a good venture for Cadence. Gotta give them credit for trying something outside the EDA product box, though. It seems they are gunning for Synopsys DesignWare IP business, and using Denali to give themselves a jump start.

Caveat: I haven't read Cadence's "EDA360 Manifesto", so I may not fully appreciate the cleverness of their overall strategy.

Will Cadence Take Away the Punch Bowl?

Big news in the world of EDA business this week, with Cadence to buy Denali for $315 million.

Though as an implementation guy, I don't use Denali products, the first things that sprang to mind are:

• $315 million is a lot of money! I think it must be one of the top 10 EDA acquisitions by price, if not top five. Anyone have list of the top acquisitions in EDA? It'd be fascinating to review the list and how those deals turned out.

  Off the top of my head guess list of bigger deals: CCT (Cadence), Ambit (Cadence), Avant! (Synopsys). Maybe ViewLogic (Synopsys), Verisity (Cadence).

• Cadence has been ambivalent or downright antagonistic toward the Design Automation Conference (DAC) in the past few years. Denali, on the other hand, is one of DAC's biggest boosters, and throws the party to attend in all of DAC. It will be tragic if Cadence clamps down on the festivities.

On a more somber note, let's hope that Cadence is able to preserve the technology and brain trust that was able to make Denali a well-established mid-level EDA vendor. Cadence has had mixed success in managing acquisitions, with some apparently not paying off (Ambit) and others holding up well (Verplex).

SCDsource & EDA technologies to watch out for at DAC 2010

The EDA/Semiconductor web site SCDsource is going away on May 7, but if you click now, you can read their preview of EDA technologies to watch out for at DAC 2010.

In the interest of preserving history, I'll list their picks here.

• Forte Cynthesizer
• Mentor Catapult C
• Wind River/Cadence Simics/Incisive Integration (Why does Cadence always have the most cumbersome product names? They must name them by committee, and everyone gets to add a word!)
• Oasys RealTime Designer
• Jasper DA JasperGold
• OneSpin Solutions 360 MV
• Magma Tekton
• Silicon Frontline F3D and R3D
• Sigrity PowerDC Thermal

iPad A4 == Intrinsity?

Wow, here's a flash, maybe Apple didn't design the "A4" brain of their iPad tablet after all: IEEE Spectrum: Evidence for Intrinsity in the iPad.

I always thought it curious that Apple supposedly pulled off such an ambitious chip with their first major in-house development. Pundits assumed that it was done with the help of Apple's P.A. Semi acquisition, but P.A. Semi had been focusing on the "Power" architecture, not ARM.

Old but Not Dead Languages

How can it possibly be that in this survey of programming language popularity, the C programming language is back at number 1 position?

I love technology history more than the average person, but I am dumb-founded that with all the software engineering development, object-oriented design, and graphical user interface work that's happened over the decades, we are relying on a language designed before many practicing engineers were born! (People may complain about Verilog HDL's crustiness, but it's "only" 25 years old.)

Though software engineering is not my principal occupation, I do enjoy programming and languages. I know "C" well enough to quickly shoot myself in the foot, but think Java is a far more elegant language. It's sort of like I've heard that Python is a better scripting language, but everyone still uses Perl.

Anyone have explanations for why "C" remains so popular? Isn't this a significant reason why computers have so many security holes? When you hear about "buffer overrun" and "malicious code execution", think "C" pointers! I can see using "C" for embedded systems if resources are very limited, but otherwise, I'm truly surprised by this survey.

SNUG's Happy Birthday

Early this month the Synopsys Users' Group conference was held in Santa Clara, California. It was a special SNUG, as it was the 20th anniversary. That's an eternity in EDA.

The conference featured record attendance (over 2,100) and a good balance of user papers on verification, implementation, signoff, and low-power design.

• Art de Geus' keynote. It's the much-anticipated "state of Synopsys" (and EDA, the semiconductor industry, and world economy).
• Award-winning papers. Congratulations to the everyone who presented a paper.
• Press Release. Includes list of awarded papers.

Automation End Game?

Thanks to EDA vendors for making hard to use and even harder to interoperate tools. I mean, what would happen to engineers if the tools were easy to use?

Engineers chime in on the A4

Or, as the VentureBeat columnist wryly put it, Apple’s A4 chip: Engineers correct stupid journalist. Some of the speculation is very plausible, and I found the anonymous quotes the most interesting of all, suggesting as reason for Apple to design their own chip

• efficiency (exactly what they need, no more)
• business/schedule
• cost: a big upfront development cost to slash the per-part cost

Some additional details, not quite as juicy, follow in How Apple’s A4 chip lets iPad run cooler, save battery life. I was most surprised at the claim from "a very trusted source" that PA Semi didn’t do the A4. It was the existing VLSI team. Could it be true? All other speculation I read was that this was the fruit of Apple's investment in PA Semi. (Although PA Semi was working on PowerPC designs, and the iPad's A4 is almost surely ARM-based.)

Scooping the MSM on A4

(That's the Mainstream Media, for those of you with lives outside of the blogosphere.) Today in the New York Times, there's a perspective on the iPad A4 chip, In the iPad, Apple Is Betting on Its Own Microchip. The analysts interviewed in the article are similarly nonplussed by Apple's chip design strategy. But the Times did snag a nice picture of the chip:

Update: Business Week's A4 story. I was never expecting Intel to be a contender for the iPad design win. And how does an analyst already estimate the cost of the A4 chip and the iPad's bill of materials? Has anyone got their hands on one outside of Apple?

Steve Jobs, Chip Wizard

This week saw a big day in the world of Technology, with Apple announcing the incredibly hyped iPad tablet. The Mercury News and The Wall Street Journal, among many others, each devoted a few pages to coverage.

As good tech consumers, we all have our opinions about the features, price point, and odds of it changing the world. Steve Jobs called it "magical". (Fake Steve says he uses neuro-linguistic programming.)

But I digress. What's the significance for chip-design engineers? Though we won't have the details from a full teardown for another couple of months, Apple did announce that they've designed the central chip in the iPad, dubbing it the "A4". Early coverage of A4 includes

• Eagerly awaiting info on Apple's A4 chip for the iPad and how its PA Semi buy fits in ... - Now Hear This! - Blog on EDN - 1750000175
• Apple-Designed Chip Marks Strategy Shift

It's intriguing that Apple has consciously decided to build an advanced chip design organization, since they are a consumer electronics company. There are comparable alternatives for single-chip mobile device computers, including the Qualcomm Snapdragon and NVIDIA Tegra. What's Apple's angle in doing it themselves? Is it just their obsessive need for secrecy? Or will they somehow integrate differentiating functions that justify the large investment and risk of running a chip design operation? It flies against the industry trend (which PC manufacturer designs its own chips?), but let's see how this plays out. I'm not foolish enough to dismiss Steve Jobs' ability to Think Different.

Anticipating the (40nm) Deluge

Image courtesy Wikimedia.

A short but encouraging news article at X-bit labs, TSMC’s Problems with 40nm Process Technology Largely Over, reports that TSMC has solved its widely-rumored yield problems with its leading-edge 40nm process. Hallelujah! This would be great news for TSMC, their customers, their customers' customers, ...

An interesting side note is the claim that at present only ATI, graphics business unit of Advanced Micro Devices, Altera and NVIDIA Corp. use TSMC 40nm process technology. Really, only three production users of 40nm? Apparently the design pipeline is getting stretched out over many generations, including 65nm on up to 130nm. Ah, I miss the good old days of 130nm design.

(Tip o' the hat to Daniel Nenni for the "tweet" tip.)

College Degrees and Career Salaries

Interesting college/career data to share with your kids (or young people who might actually listen to your advice).

Best Undergrad College Degrees By Salary

Methodology Annual pay for Bachelors graduates without higher degrees. Typical starting graduates have 2 years of experience; mid-career have 15 years. See full methodology for more.

Best Undergrad College Degrees By Salary

The Glass is Half ...

Saw a couple of interesting blog posts/articles recently. Daniel Nenni's data-rich 2010 Semiconductor Forecast made me feel quite bullish about the near-term prospects for our industry. Update: EE Times' Top 25 predictions for semis in 2010 are specific and considerably more dour than Mr. Nenni's forecast.

The other is ominous for the long-term: Is Moore's Law near its end? - Now Hear This! - Blog on EDN. But really, running out of steam in less than five years? Be sure to read the comment stream, as there are some good additions there.

My perspective is that a near-term uptick is certainly overdue. By all indications, the US economy is starting to recover, and with it, consumer spending on electronics will get a nice boost. There's certainly a lot of innovation being shown at the Consumer Electronics Show this week.

As for Moore's Law, I think it keeps working as long as we're using planar CMOS. If we have to transition to fundamentally different materials, or 3D structures, all bets are off.

Mordac is alive and well ...

Apparently Dilbert's "Preventer of Information Services" has taken Core Concepts of Information Systems Security, X52.9380 and is thriving at Synopsys.

Can you tell I had to reset my SolvNet password today? Does Synopsys really hate customers this much? My feelings haven't changed since I last changed my password.

A Secure Job

As attacks increase, U.S. struggles to recruit computer security experts raises an intriguing career possibility for engineers with a solid grounding in computers and networking. I wonder what's required to become a bona fide security specialist?

I'd like to to wish you all very happy holidays, however and wherever you celebrate them. With the recovering economy, may we all have a happy and prosperous 2010.

CS Gravitas

It's hard to imagine greater evidence of a tremendous impact on computer science than authoring the most cited paper in all of computer science as well as in EDA. Remarkable! Before you follow the links, can you guess the subject of the paper?

Find the answer in Gabe Moretti's Kaufman Award Dinner Notes. Good links and amusing pictures are in the coverage at SCD Source. And to delve deeper into the subject, see the Wikipedia article.

Building Blocks of EDA

Some of the unsung enablers of EDA innovation are the companies providing building blocks for common infrastructure tasks. Especially if you're a startup trying to bootstrap an innovative algorithm idea, it's crazy to develop yet another HDL parser or schematic viewer. I was reminded of these products as I read the latest press release from Verific Design Automation, which produces rock-solid HDL front ends for a number of commercial and in-house EDA tools.

The original player in this market was Interra Systems. A great schematic front end is GateVision, available from Concept Engineering. Are there any other major infrastructure providers I've overlooked?

That Light at the End of the Jobs Tunnel

Recently I posted some hopeful anecdotes about the job market for semiconductor design engineers.

Now I read Tech layoffs continue, despite signs of economic improvement and it makes me feel my prior observations are the exceptions to the rule. What's your sense of the current job market? I'm hoping that my new found pessimism represents "capitulation", that point when hope is lost, and marks the nadir of a market or trend.

Engineering Halloween

He only pokes fun at Marketing a little bit this time.

I must confess, I once dressed as an integrated circuit for Halloween. It was in college and I was a DIP. Maybe that's why it didn't impress the girls? Have a great weekend.

Are You Listening?

When I'm out and about doing chores or exercising, chances are I'll be listening to my iPod. But more often than not, I'm listening to podcasts rather than music. Listening to podcasts is an efficient way of "reading on the go". You can catch up on the latest news stories, political opinions, or investment ideas. Those are my interests; you can find a podcast on practically any topic.

Have you listened to podcasts? Which are your favorites? In our field of semiconductor engineering, there's not a wealth of content. But here are some of my favorite engineering/technology podcasts to get you started.

1. IEEE Spectrum Podcast, which is described at Podcast Picks.
2. Science Friday by Ira Flatow. A classic high-quality program from NPR.
3. Security Now by Steve Gibson and Leo Laporte. It's mainly about computer security, but you can also learn the latest on PC software and networking by listening.

It's easiest to subscribe through iTunes, but there are other ways using the RSS feed and a "podcast catcher" program. Happy listening!

Synopsys Users' Group CFP

As you may have heard me say (write) before, the Synopsys Users' Group (SNUG) conference is the most useful conference I attend each year. If you're involved in chip design and haven't attended, you really need to check it out. There are conferences around the world, but the biggest one is in Silicon Valley every March.

Why am I bringing this up now? Because the Synopsys Users Group - San Jose Call for Papers is open! Here's a chance to show your chops and burnish your resume by demonstrating the cool stuff you're doing with Synopsys tools. The authors get a lot of support from the experience Technical Committee [full disclosure: I'm a member] to help develop their presentations and papers. Think about it, and I'll see you at SNUG.

Career Thoughts

Image courtesy Wikimedia.

Taking a break from the technical, career issues merit reflection and discussion. Here are some brief thoughts.

How's the Market?

What's your perception of the ASIC/EDA jobs market? My take is that it's pretty weak, but a number of companies are "selectively hiring". I had a couple of friends leave their struggling design services firm, and they were able to land jobs at established growing companies within a couple of months. On the other hand, there are plenty of engineers who have been looking for many months.

One differentiator is that hiring favors leading-edge experience (e.g., expert P&R and design closure of 65 or 45nm chips), or knowledge (e.g., advanced degree with an emphasis on an emerging hot area).

Natives Say No

With the depressed job market, this isn't the best time to wonder about this, but I'm perplexed at the lack of US-born chip design engineers. Of course, it stems from the lack of US-born engineering graduates. This leaves me scratching my head--engineering jobs are not THAT bad. As a matter of fact, they're one of the fastest ways to earn a very good paycheck out of college, with intellectual challenge to boot.

A downside is that engineering isn't the most secure career around. There are regular risks of downsizing or technological obsolescence. It's not a cushy career, but how many are in this age of globalization?

If you want a secure career, at least medicine and law are "less outsourcable". However, if you really want societal respect, security, and a guaranteed comfortable retirement, I recommend becoming a fireman.

Give US Your Best and Brightest

In the US, we are so fortunate to attract many of the best and brightest scientists and engineers from the rest of the world. There can be complaints about "H-1B abuse", but there needs to be a system that allows the country to benefit from the great contributions possible from immigrants with advanced degrees.

Where Do Seasoned Engineers Go?

While I'm not there yet, friends and I do wonder where all the full-career engineers are. Look around you -- do you see many 50-something engineers? I don't, and I wonder. Do they all transform into real estate agents? Or should I worry about a future as a Walmart greeter?

Others Weigh In

1. As I was preparing this post, a timely and provocative article appeared in EE Times, U.S. engineers at a disadvantage . The discussion in the comments is fascinating.
2. Update: Harry the ASIC Guy and his commenters weigh in on outsourcing, and IBM's aggressive program in particular.
3. Update: Lou Covey has analysis and advice at We're in this boat together. Start acting like it.

Everybody's Getting Physical

Image courtesy Wikimedia.

Back before "nanometer design", there was "deep submicron design", and ASIC synthesis users became very concerned about interconnect effects on timing. The first attempt to deal with this was through "Links to Layout", and especially a whole slew of custom wireload model (CWLM) strategies. If you look at SNUG programs a number of years ago, there were more CWLM papers than you could shake a stick at.

A major advance in accounting for interconnect effects was when synthesis tools started to perform "virtual layout" as part of the optimization-estimation-timing analysis loop. The most notable tool to do this was Synopsys Design Compiler Topographical. My colleagues and I did evaluations of DCT starting with 90nm designs, and data indicated better correlation and generally a better netlist for Place & Route.

As we progress from 90nm to 45nm and below, physical considerations are becoming ever more sophisticated. The latest examples are

• Synopsys Design Compiler Graphical. Includes congestion prediction and some congestion relief algorithms.
• Cadence RTL Compiler's New "Spatial Technology", the latest physically-aware RC feature.
• Oasys RealTime Designer. "RTL physical synthesis."

The Skeptic Weighs In

While "getting physical" has the feeling of more accuracy and general goodness, TNSTAAFL. Though I hope for better quality of results and predictability, I see the following drawbacks

• It forces the logic designer to learn physical design details, and learn new tools or coordinate with a physical designer. While that's nice to know, it takes away from the RTL creator's time to focus on architecture, design and verification.
• The optimization process itself will either take longer (to perform the "virtual layout"), or results will be less-optimal, because optimization time will be taken away in order to run physical algorithms.
• Some of the effort may be wasted, especially for detailed buffering and gate sizing. For example, some P&R tools "throw away" the incoming netlist's buffering and sizing, and re-optimize in the physical domain. So, that effort in logic synthesis is wasted (other than its predictive benefit).
• While WLM-based synthesis is well understood and mature, these physical tools are not. It may take a long refinement period for the tools to produce reliable netlist quality and consistency.
• Some of these tools can't decide if they're logic design tools, physical design tools, or some mish-mash of both. In their efforts to be accessible and affordable for logic designers, they may lack the physical design functions and data access needed to do the job right.

Over the coming months, advanced synthesis users will be putting these latest tools through their paces with real designs. And we'll start to learn whether the added complexity and cost leads to better implemented designs. If not, we can always go back to our old friend the wireload model, trying to get to P&R quickly, where the rubber really (not virtually) meets the road.

Update: I stumbled upon a detailed reply/rebuttal over on the Cadence Logic Design blog! Jeffrey Flieder, thanks for writing this. I very nearly overlooked it.

Found at DAC

My pre-DAC post Looking Forward to DAC laid out what I hoped to investigate by visiting exhibitors, namely

• Low Power
• Datapath
• MCMM
• parallelism
• Asynchronous Design

Well, despite my best-laid plans, I wasn't able to check all these items on my list in two days of roaming the exhibits floor. In some cases (i.e., Asynchronous Design), I didn't find an appropriate vendor. In other cases, my schedule or the vendor's appointment constraints didn't allow me to gather the information. But DAC was a great opportunity to see many vendors, and by careful plan or happy accident, I was able to visit many interesting companies. I'll group my vendor impressions into these categories:

High-Performance Design

• It seemed like Oasys Design Systems was the most talked-about implementation vendor at the show. As I've said before, their capacity and run time claims are incredible. At this show, they put a lot of emphasis on making their claims credible. They've got some customer testimonials to validate them, and their closed-door demo suite explains what's revolutionary about their physical synthesis approach, and why it could be dramatically faster than today's synthesis tools. Update: Harry the ASIC Guy explains technical details of Oasys' approach.

  And to top it all off, I just about ran into Joe Costello on the DAC floor. (He was suspiciously near the Synopsys booth at the time.) It should be great to have Joe back in the EDA industry. I like and respect Aart de Geus a great deal, but Joe Costello can add motivation and excitement back to an industry that's feeling tired.

• Micro Magic is an interesting small design/tools company that's been around almost 15 years. Because DAC wasn't very crowded on Wednesday, I could walk into their booth and have a long informal chat with their CEO. He exudes confidence and credibility.

  One of their tools is a Datapath Compiler, which is one of the few commercial solutions for maximum performance datapath design. Other companies have come and gone (Arcadia is long gone; Arithmatica wasn't at DAC), but Micro Magic apparently has numerous real success stories. (Their customers seldom allow themselves to be named.)

• iNoCs is an early stage startup with tools to synthesize Network on Chip (NoC) IP. Their debut was especially timely because NoC was one of the technologies featured in the Wednesday Keynote by Bill Dally, Stanford professor and NVIDIA Chief Scientist. As it turns out, the connection is even stronger. iNoCs is advised by noted EDA professor Giovanni De Micheli, who has been a colleague of Professor Dally.

Parallelism

• The only company I met with a heavy focus on new parallel computing products was ACCIT, which is developing highly accelerated SPICE simulators running on ATI GPUs. Looking forward to the NVIDIA CUDA port, guys!
• Of course, many of the big EDA vendors are adapting their products for multi-core technology, for example Synopsys PrimeTime Multicore.

ESL Synthesis

I spoke to a few vendors in this space, but I wouldn't dare pretend to have a good grasp on where the field is at. Several journalists and bloggers are writing "now is the time for ESL synthesis", but I have yet to meet the designers using it or even enthusiastic to get into it. It's puzzling to me. There apparently are specific domains with considerable success, such as wireless and image or video processing. And there are specific geographic areas adopting it first, namely Japan. But for the mainstream ASIC designer, I don't yet see it catching on.

Others

I liked what I heard in a brief visit with Imera, which develops hardware+software solutions to allow secure remote debug of software (e.g. EDA tools). In my work, there is constant antagonism between the EDA vendor, whose engineers claims they cannot debug their software beyond their walls versus the EDA customer, which doesn't want the "company jewels" of full-chip RTL or netlists to ftp over to the EDA vendor. Imera has solved the problem with a distributed debugger and networking solution that allows the R&D engineer to debug from the vendor side, while the EDA tool is running on the design data at the customer's site. Sounds like it would resolve the stalemate and allow us to get on with the problem-solving.

Overall Impressions

I had not attended DAC since 2006. It was a little disorienting because of all the changes in the industry and the conference itself. Attendance was way down from boom times. For the first time, I had an "exhibits only" pass, which allowed me to go up every day and visit the exhibits floor but not the technical program. After Free Monday, the floor was much less crowded, and it was a pleasure to walk right up to any vendor and get all my questions answered. One irritating practice of several vendors was to not have any open demos, but to require a one-hour appointment to be scheduled for a closed-door meeting. I found this quite inconvenient for any sort of spontaneous discovery, and as a result both vendors and I missed out on some worthwhile discussions.

I was glad I attended DAC. I obtained information that will help me in my job, and met old and new friends. I wish for the sake of the organizers and the exhibitors that attendance had been stronger, but the economy was a strong tide to fight. Let's hope that tide is turning and the 47th DAC in Anaheim will celebrate a growing vital EDA industry.

DAC Meta-Blogging

If you're at DAC and haven't yet overdosed on "Social Media", please stop by Tweet, Blog or News: How Do I Stay Current? this afternoon. I'll be on the panel, sharing ideas for how to wade into this trend in the most efficient way. Listen, ask questions, and say Hi.

Denali Software is a great supporter of DAC. They teamed up with Atrenta and Springsoft to start the I Love DAC program and provide dozens of complimentary Exhibits passes for the conference. They also ran good-natured competitions for EDA's Next Top Blogger and EDA's Community Superheroes. Congratulations to Karen Bartleson of Synopsys for winning the Top Blogger distinction, and Joy Matsumoto from Cadence for her great efforts to support charitable causes.

The Road Less Traveled

DAC begins its second full day in San Francisco, and I encourage you to take advantage of the opportunity. I was up there yesterday and found a great variety of vendors, panels, and other events to check out. In the morning, crowds were pretty sparse, but there was a definite pick-up in the afternoon. In particular, there was a lot of congestion around the prominent Synopsys booth, next to a well-visited Standards area.

Fellow blogger JL Gray in front of Twitter Tower (image courtesy jlgray)

Synopsys is diving into "Social Media" in a big way at DAC, so it's worth checking out Conversation Central with its variety of sessions on how to understand and make the best use of these new communications media. The Twitter Tower is a novel way to take in DAC's zeitgeist.

That said, I'd encourage everyone to venture out beyond the comfort and safety of the big EDA vendors! If anything, I de-emphasize visits to the top vendors, because one can follow their announcements and arrange meetings any time of the year. But DAC is a unique opportunity to see a great variety of vendors, from the "second tier" specialist that you're not quite familiar with to the Mom & Pop startup that just rolled out their shingle for their first DAC. To make this discovery more purposeful, I flip through the Exhibitor descriptions in the DAC program and highlight the booths of companies that sound remotely interesting. That way, you can avoid wasting time by ping-ponging between North and South halls. Go for it!

On a lighter note, on Sunday I made my way to San Francisco for an EDAC reception. Before that, I explored Golden Gate Park (stunning!) and snapped a few pictures.

The first perplexed tool user.

Real-Time DAC Tweets

The next best thing to being at DAC is to watch the "tweets" posted by attendees--

Getting to DAC

There has been no end of posts about "going to DAC", what to see, what's hot, etc. But, how to actually get to the venue? Since I'll be making the trek solo from Silicon Valley and am phobic about the hassle and expense of driving and parking in SF, I'll share some public transportation research.

Caltrain

Caltrain provides service on the San Francisco Peninsula. Here's their schedule. If you catch one of the "baby bullet" express trains, it's less than an hour from San Jose to San Francisco. Fares from San Jose are

One Way	$7.75
Day Pass	$15.50

From the Caltrain station in San Francisco, you'll need to get to Moscone Center. In previous years, DAC ran a shuttle for this, but I don't see any notice of it this year. You can either walk or take the city bus. It's only a one-mile walk, so I plan to try this and count the back and forth as my exercise for the week. Google has a nice map showing both the walking route and links to bus schedules, if you prefer. View Larger Map

BART

Bay Area Rapid Transit has stations on the Peninsula and East Bay (Fremont is nearest to Silicon Valley) and can take you to Montgomery Station, only 3.5 blocks from Moscone Center. The One Way fair from Fremont to Montgomery Street is $5.60.

Synthesis Gets Interesting

As a pleasant surprise, there's quite a bit of activity and emerging excitement in the area of synthesis, just in time for this year's DAC.

Physical Synthesis

Oasys Design Systems has come out of stealth mode with rather incredible performance claims.

It's exciting to hope for a revolution in synthesis. Put me in the "show-me" camp. It's (relatively) easy to meet 80% of what Design Compiler can do, but there are many features and tricks developed by DC over the years, making it a hard tool to displace. Synopsys has certainly seen strong competition, including from Ambit BuildGates (acquired by Cadence) and most recently by Get2Chip (now Cadence RTL Compiler). What often happens is not that king DC is overthrown, but that the competition lights a fire under Synopsys and their tools will improve at a much faster pace than market dominance would dictate.

What's interesting about Oasys are the tremendous claims about capacity and run time, and the emphasis on physical synthesis, combining logic synthesis with placement and optimization. The company also has impressive board members, including Sanjiv Kaul (former implementation GM at Synopsys) and, re-appearing to EDA after a long hiatus, Joe Costello (charismatic and successful former Cadence CEO).

ESL Synthesis

For several years, EDA industry analyst Gary Smith has been calling for the ascent of ESL (Electronic System Level) design. He was already called an ESL evangelist back in 2006! It's been the next big thing for a while now. It seems to follow the industry's progression from transistors to gates to RTL, but RTL remains the mainstream design method.

In the context of design implementation, ESL implies synthesis at a more abstract level than RTL. This year, there appears to be considerably more buzz, and not just from Gary. See, for example, recent posts by John Cooley and Richard Goering.

Key players include

• Forte Cynthesizer
• Mentor/synthesis CatapultC
• Cadence C-to-Silicon
• Bluespec
• Synfora Pico Extreme

My apologies for any I've overlooked--I'm learning about this field. One point of concern is that there isn't a consensus on design language/dialect, which varies by vendor over C, C++, SystemC, and proprietary languages/extensions. That can impede adoption. It was Design Compiler that established the de facto standard for Verilog RTL synthesis subset, and this provided a common point for customers (and competitors) to converge on.

It's nice to see continued innovation in this critical area of IC design, and merits further investigation.

Looking Forward to DAC

As most everyone is aware, the big conference in the chip design software world, DAC, runs July 26-31 in San Francisco. I'm looking forward to it and plan to be up there most days. Some prognosticators have posted their "must-see" lists. (Gary Smith, John Cooley laying out the law for aspiring vendors) and there will be more to come.

Rather than calling out specific companies, I'll share some of technologies that I'll be looking to learn more about.

Low Power

This is one of the genuinely valuable and necessary "next big things" in methodology.

Datapath

I've always been surprised that specialized datapath techniques aren't more successful. It seems like you either use an advanced RTL synthesis tool, or design datapath by hand. There's not a lot of in-between.

MCMM (Multi-Corner, Multi-Mode)

It sounds like the solution to many problems. But how well does it really work -- how scalable is it?

parallelism, multi-threaded, multi-core, GPGPU

How will EDA ever catch up to designs scaling by Moore's Law? By using the parallelism available in today's CPUs and GPUs. Multi-core is working today for 4-8 cores, but may hit a wall beyond this. And what about the tremendous parallel computational power in your Graphics Processing Unit? A few EDA tools are leveraging the CUDA platform; where will it pop up next?

Update: check out Richard Goering's interview with EDA luminary Kurt Keutzer on this topic.

Asynchronous Design

This is my token research-y interest. Synchronous design is what we all learn in school, and there's a plethora of tools (namely, the EDA industry) to automate such designs. But there are drawbacks with respect to area and power. Can we learn a new way to design, and develop new sets of IP and automation tools?

You Probably Believe We've Landed on the Moon, too

Don't believe everything you read. There's an insightful behind the scenes exposé on DeepChip about a technology web site that turns out to be a marketing venue for a group of EDA start-ups. Nothing wrong with that, but the disclosure of who's behind it took some digging and questioning to tease out.

Of course, one would be naive to assume this doesn't happen elsewhere in the media. Even Mr. Cooley's beloved DeepChip, with its purported user-generated content, can be gamed. When you read a glowing endorsement of an EDA tool, ask yourself questions such as

• Who wrote this? Are they "anon"?
• Did they really write it? Or could it have been "ghost written" by the EDA vendor and submitted in the customer's name?
• What is the author's interest in the vendor? Does the author's company have a financial or other interest in the vendor's success?

Nothing beats the testimonial of someone you know and trust, other than your own hands-on evaluation.

p.s. in honor of Apollo 11's 40th anniversary, read more about Apollo Moon landing hoax conspiracy theories .

DAC Appeals to Users

When I first started attending DAC (1990 in Orlando), as an ASIC designer who'd recently joined an EDA group, I found it disorienting. The exhibits floor seemed like a circus with attendees rushing from one booth to the next to collect the best schwag (some things never change). I dutifully sat in paper presentations that sounded interesting, but I soon realized they weren't addressed to designers or users. I came to think of them as "PhD theses showing a routing algorithm that performed 13% better on an academic benchmark". Not to belittle those papers -- the mathematics and rigor impresses me greatly, but I don't understand all of it or apply it in my job.

Over the years, DAC has become more user friendly. The panels in particular are often informative and sometimes provocative. I find that I'm getting more and more out of DAC.

This year, there's an explicit "User Track" at the conference. I'd like to share a description of the User Track while presenting the first guest post on John's Semi-Blog. Please enjoy!

User Track at DAC:  Learn from Your Peers

Soha Hassoun
Tufts University
46th DAC Design Community Chair

Leon Stok
IBM
46th DAC New Initiatives Chair

Today’s connected world makes it possible for you to work from everywhere.  Yet, there’s only one place where you can learn how your peers successfully applied design tools to chip design and where you can exchange valuable experiences:  the new User Track at this year’s DAC.

The three-day User Track features 40 presentations that run in parallel with regular technical sessions.  Speakers include expert designers from Cisco, ClueLogic, Fujitsu, IBM, Infineon, Intel, Qualcomm, Samsung, STMicroelectronics, Sun, Texas Instruments, Virtutech, Xilinx and others.

Identifying Front-End Challenges

Power planning and verification continues to be hot.  A team from NEC will detail an automated flow to pre-characterize the power consumption of a set of basic components starting from their behavioral description in C, down to their power estimation at the gate-level netlist.  A team from Cisco will describe the use of a power noise analysis tool to analyze system power integrity.  Engineers from Texas Instruments will illustrate how they used an EDA tool to integrate complex multi-power/voltage domain design.  Intel engineers will present a flexible, high-level power management modeling and simulation framework for power architects.  And, a team from STMicroelectronics and ST-Ericsson will outline an exploratory and refinement-based power planning system.  Also, Intel engineers from India and Israel will offer a novel direction for using abstract executable models to verify power management protocols.

Tackling Backend Challenges:

In the Practical Physical Design session, a team from Intel will discuss how they tackle ECOs as late logic changes delay the process and register arrays occupy more than half of all transistors of modern designs.  Qualcomm designers will describe how they build their semi-custom methodology and STMicroelectronics engineers will outline e how they use the IP-XACT standard from Spirit to enable IP reuse.

Accurate power supply and substrate noise analysis remains a challenge, and practitioners from Qualcomm, IBM, Samsung and Kobe University will show how they attack the problem.  Texas Instrument designers will show how to analyze blocks for reuse in multiple metal stacks.  Intel engineers will highlight their approach to assessing design feasibility early in the process to avoid problems later.

A team from Stanford University, Rambus and Netlogic describes a way to tackle analog reuse as it becomes as important as reuse is in digital design.  A group from Cadence and several Taiwanese universities will describe their approach to integrate MEMs in mixed-signal designs.  Engineers from NXP and Magwel tackled the problem of analyzing substrate noise and will present their results in 90nm process technology.  With complex circuits often needing an integrated approach to physical and electrical verification, a team from SysDsoft and Mentor describes how they accomplished this on their designs.

In addition, join us for an Ice Cream Social Wednesday from 1:30pm-3pm where 42 posters will offer an opportunity for you to mingle with other EDA tool users. 

Access to the User Track is included with the full-conference registration.  Or, register separately for the User Track and get access to the keynotes, in addition to the User Track.  For more details, visit:  www.dac.com.  We look forward to seeing you in San Francisco.

###

For more information:

Nanette Collins

Publicity Chair, 46th DAC

(617) 437-1822

nanette@nvc.com

The Year DAC Changed Forever

There is so much good DAC material coming out; EDA is hitting critical mass in the blogosphere. There's a new social network site "I Love DAC" that ramping up, where I was delighted to see this flashback from the heydey of EDA: 1991: The Year DAC Changed Forever - The DAC Fan Club. (props to Steve Leibson)

Not only is the video entertaining, but it's a bona fide piece of EDA history. It's also worthwhile to reflect on the promise of Frameworks, still unfulfilled in EDA: seamlessly integrated multi-vendor tool flows. Well, at least it's job security for CAD engineers.

Denali DAC Festivities

The EDA company Denali is famous for their DAC parties. They are also running fun contests where the public can vote for the top EDA blogger or community superhero. See some new faces and vote for your favorites at

• EDA’s Next Top Blogger
• Community Superhero

And, at the party itself, watch the show and vote for EDA Idols!

DAC Attendance Deals

According to John Cooley's DeepChip site, Atrenta, Denali and Springsoft will be sponsoring 600 free DAC Exhibit Hall passes this year.

John also posted that the very popular "Free Monday" deal is coming back as well. Here's what his email described:

From: Bob Gardner [bobg=user domain=edac.org]

Hi, John,

Please inform your readers that EDAC has decided to sponsor the return of "Free Monday" to DAC this year. If they want to take advantage of this "Free Monday" registration, your readers must go to:

http://www.deepchip.com/FreeMonday.html

and complete all four pages of the registration. On the THIRD page they'll find a newly added "Free Monday Exhibits" option -- they MUST check this box to get this special registration.

On the forth page they should see a web receipt with their unique bar code confirmation on it. They must print this entire page.

To enter the DAC Exhibit Hall on Monday, July 27th, the engineer must present a paper copy of his/her entire bar code page to the Advance Registration desk located in the North Lobby of Moscone Center.

See you at DAC, John!

- Bob Gardner EDAC San Jose, CA

As for me, I've already paid my $50 for the all-DAC exhibits pass. See you there. The buzz for DAC is heating up, so watch for more blog posts before the conference.

DAC on Sale

Just a quick reminder: DAC 46th Registration Rates go up after June 29, so register today to get the early discount. See you in San Francisco!

Sean Interviews Rajeev

Though he's not as colorful as Gerry Hsu, Rajeev Madhavan, CEO of Magma Design Automation, is one of the most interesting and outspoken executives in the EDA industry. Check out Sean Murphy's Interview with Rajeev.

Rajeev founded several significant EDA companies, was apparently out-manuvered in the board room at times, and is forthcoming with what he's learned about the EDA industry and building companies.

EDP 2009 & the Return of ASIC

Electronic Design Process 2009 Symposium Program has links to the presentations from this April workshop in Monterey. I've never gone before, but it looks relevant and interesting.

I glanced at a few presentations and was most surprised to see predictions of the resurgence of ASIC vendors (vs. today's popular "COT" model). I'm not sure I agree, but it makes a certain amount of sense. It takes a lot of tools, people, and expertise to implement 45 nanometer chips. The proposition is that if it is possible to cleanly hand off at RTL, then the chip designer can focus on functionality, and let an implementation house focus on the tricks and traps of nanometer-scale design closure. But that's a big if, to be confident that the hand-off is of a properly constrained and realizable design!

Rumors of Usenet's Death Not Exaggerated

Today, I received notice from my Internet Service Provider, att.net, that they will no longer provide access to the Usenet service. This development saddens me and brings back memories of how incredibly useful Usenet was in the early days of the Internet (even pre-Web).

You could find kindred spirits of any interest available for text-based correspondence and enlightenment. I solved countless software problem (including both Windows and Linux) by searching through these groups. Who could forget groups like

• comp.cad
• comp.cad.cadence
• comp.cad.synthesis
• comp.lang.verilog
• comp.lang.vhdl
• comp.lsi.cad
• sci.engr.semiconductors

Oh, and the flame wars! (I remember there was a character outraged over the Ottoman Empire who sought to cancel every post containing "turkey", which swept up Thanksgiving recipes, as well.)

The beginning of the end was when Web access took off, epitomized by "AOL newbies" pouring onto Usenet without regard to the collegial etiquette that previously existed. After AOL, there was overwhelming growth of users, which strained the scalability of worldwide discussion forums. Finally, the death knell: Spam. When I peek at Usenet groups today, they're full of the most crude and amateurish spam. It appears that posts are not run through filters as is all of our email, and this makes the noise/signal ratio unbearable.

R.I.P., Usenet. You were one of the forefathers of what we enjoy today through the Web, forums, IM, and social networking.