John Cooley is the original user's voice in EDA, and his DeepChip web site and mailing list continue to have the biggest following. I used to think of John as "the Michael Moore of EDA" -- a rabble-rouser, confronting the dominant companies and their executives, and sticking up for the little guy.
He still has that image, but I've come to realize that the in-depth tool evaluations that he posts aren't always the innocent sharings of chip engineers that they appear to be. There's definitely an element of the EDA vendors' PR machines in some write-ups. That's OK, as long as you take them as such. If these articles are really EDA vendor white papers or press releases, at least they're written in a language that speaks directly to the challenges we face in chip design. With that caveat, here's a list of his latest nuggets:
- Rumors on Synfora, Forte, CatapultC, AutoESL, CoWare, Calypto, EVE. This doesn't read like EDA vendor spin, but rather some provocative EDA-insider scoop on M&A in the ESL space.
- A follow up first evaluation of Atoptech's new Apogee floorplanner
- Another production user on NextOp's BugScope assertion synthesis
- Some hands-on user experiences with HLS and AutoESL's AutoPilot
- Getting 100X scan compression with Talus Design and Mentor Tessent
- Cadence Virtuoso and Solido for variation-aware custom design. (clearly labeled as a white paper)
- Whitepaper on IC Manage unifying bug tracking & design management. (clearly labeled as a white paper)