I got to wondering -- which tool has the biggest lock on a major piece of the EDA tool constellation? (I originally wrote "monopoly" instead of "franchise", but don't want to connote market manipulation.) From my perspective, three come quickly to mind
- Cadence Virtuoso
- Synopsys Design Compiler
- Synopsys PrimeTime
You may have other ideas, and I'd love to hear other nominations. Of these three, I think a good case can be made for Design Compiler having the strongest position. The other tools have large market shares, but also competition determined to make inroads.
Who might chip away at the synthesis gorilla? The old and new rivals are Cadence RTL Compiler and Oasys Real Time Designer. Just published on ESNUG is this "marketmonial" (I need a word for a marketing-inspired testimonial): DeepChip.com: "An Oasys RealTime Designer vs. SNPS DC-Topo/DC-Graphical benchmark . A couple of things that I especially like about Oasys' approach:
- If Oasys truly optimizes at a higher level of abstraction (physical feedback can change the way RTL structure is synthesized), then substantial performance advantage claims become believable
- It freely exports DEF and integrates with the physical design world. By contrast, DC Topographical/Graphical can't decide whether it wants to be complete physical synthesis or "PD-lite", not fully supporting or integrating with detailed physical design data. (RTL Compiler is open like the Oasys tool in this regard -- it interfaces with Encounter P&R tools using standard data exchange formats.)
Time will render the verdict, and the EDA battlefield is littered with past attacks on DC's franchise, but we need competition in all tool areas to continue advancing the state of the art.