Collusion Happens

Synopsys F3Q2010 Earnings & Focus

I don't read all the EDA companies' investor reports and analysis, but the transcript of Synopsys CEO Discusses F3Q2010 Results - Earnings Call gives you a concise view of Synopsys' recent successes and future emphases.

Top themes:

• IP. The DesignWare team is chugging along with significant and growing business, augmented by the Virage Logic acquisition.
• Systems
• FPGA Prototyping

Product-wise, Aart emphasized their custom design competitor to Virtuoso, which I don't find super exciting. It's always nice to have a more modern implementation of a workhorse tool, but not earth shattering. Synopsys bread and butter tools, which pay the paychecks, didn't get much air time.

I think some of the market share claims could be misinterpreted (90% of 32 nanometer chips), but that's standard fare for the ways vendors advertise this.

Rethinking Digital Design

Famed Stanford professor Mark Horowitz is giving talks on Why Design Must Change: Rethinking Digital Design. The questions raise provide refreshing distraction from the day-to-day concerns about the economy, lack of growth in EDA, and creative destruction in the semiconductor industry.

Prof. Horowitz's solution is provocative and plausible, though not a "slam dunk". I'd like him to quantify how much his approach would reduce the total cost of nanometer semiconductor design. Also, how applicable is it to domains beyond processors? Isn't it very difficult to create an "architecture generator" for each domain? For another perspective, here's a blog post reviewing the talk.

Best Companies To Work For

The 25 Best Tech Companies To Work For uses data from Glassdoor.com to aggregate the anonymous, inside scoop on what's good and what's not at employers.

Companies on the list relevant to EDA/ASIC engineers:

• #1 Google
• #4 Apple
• #7 Qualcomm
• #12 Juniper
• #14 MathWorks
• #15 Analog Devices
• #17 Intel
• #22 Synopsys "employees love their CEO"
• #24 Cisco Systems
• #25 Texas Instruments

Moore's Law for EDA?

Thank you, EDA vendors! From Semiconductor input costs vs output prices -- managing the squeeze:

SURPRISE: EDA cost per transistor is coming down the same learning curve as all the other input costs like materials, chemicals, labor, etc. (above) and it has been doing so throughout semiconductor history.

What is Wally Rhines' prescription for increased EDA value-add (and profits)? EDA vendors

... must incorporate the embedded software development and system analysis costs into their design tools and flows. To the extent this is accomplished, there isn’t a cost problem and the 30%+ per year per transistor cost reduction can be achieved. That’s why EDA companies first became involved in embedded software in the mid 1990’s. That involvement will grow as EDA companies take on more responsibility for the total design challenge and its costs. It’s just part of the evolution of roles in the semiconductor industry. (Walden C. Rhines is chairman & CEO, Mentor Graphics Corporation.)

Although in the short term there are still plenty of us fighting it out for nanometer-scale timing (and now power) closure, the focus on software and systems is plausible for the long term. We must find quantum leaps in productivity to take advantage of Moore's law in semiconductors.

SKMurphy's DAC 2010 Meta-Post

Sean Murphy has done a great service in compiling much of the Design Automation Conference coverage in his DAC 2010 Blog Coverage Roundup. It merits close review, and is an especially welcome resource for people like me who weren't able to attend the show.

You can see other trip reports and interesting links in the delicious.com sidebar of my blog, where I post EDA and Semiconductor links.

Spying DAC from Afar

Vendors to See, Vendors to Overlook?

I don't mean to become a "riff on John Cooley" blog, but it turns out he's pumped out some provocative missives leading up to next week's Design Automation Conference (DAC). I was about to write a post on "what I'd see at DAC", when along came Cooley's Cheesy Must See List for DAC 2010. Before we review his list, let me offer my own list of interesting products and technologies. This won't be as expansive as John's list, since I spend most of my time using or considering implementation tools.

Intriguing Products

• Magma Tekton. The tool is targeted to be a better, more modern PrimeTime. Usable as a drop-in replacement, with claimed significant speed and capacity advantages, and attractive added features like SPICE integration and MCMM analysis.
• Oasys RealTime Designer. I wrote about Oasys last year, when they came out of stealth mode. Now, they're rolling out customer testimonials from Xilinx and Juniper Networks. Harry the ASIC Guy, who's been around the EDA industry, has some interesting theories about where Oasys may find business.

Interesting Technologies

• Silicon IP. This is the most sure-fire way to develop 45nm and 28nm chips in an economical way. But do you want to become the general contractor for a dozen IP vendors? You may not have to, with consolidation such as Cadence acquiring Denali and Synopsys acquiring Virage Logic.
• ESL. It's always seemed like a logical step up the abstraction ladder to rise above RTL. There's lots of M&A activity here, with Synopsys and others gobbling up ESL synthesis companies.
• Variation-Aware Analysis. Will SSTA ever be ready for prime time? It's been the Next Big Thing in EDA for a few years, but there is little PT-VX talk at SNUG, and most of the STA startups are focusing on beating PrimeTime at traditional corner analysis rather than SSTA.
• Asynchronous Design. I'm intrigued by not having to synchronize a clock across a chip, and hardening cross-chip interfaces to variation. But I've seen little in the way of IP or automation to realize such unconventional design techniques. Are there any vendors out there? Who are the academic research leaders?

The Cheesy List

I do admire John Cooley's list for its breadth. For the most part, I think he hits the major players in each area and captures the talking points that they're featuring for this DAC.

With one notable exception. Did you notice that his list doesn't feature a certain EDA company that's hard to overlook? That's right, Synopsys. He doesn't feature one Synopsys product in his list! That's a curious oversight to me. While I do think that much of EDA innovation comes from smaller companies, Synopsys does hold its own in innovation compared to Cadence or Mentor, but those companies did have featured products in John's list. Are John and Synopsys having a spat, or is he getting ready to roll out his exclusive must-see Synopsys list?

Pre-DAC EDA Gossip and "User Evaluations"

John Cooley is the original user's voice in EDA, and his DeepChip web site and mailing list continue to have the biggest following. I used to think of John as "the Michael Moore of EDA" -- a rabble-rouser, confronting the dominant companies and their executives, and sticking up for the little guy.

He still has that image, but I've come to realize that the in-depth tool evaluations that he posts aren't always the innocent sharings of chip engineers that they appear to be. There's definitely an element of the EDA vendors' PR machines in some write-ups. That's OK, as long as you take them as such. If these articles are really EDA vendor white papers or press releases, at least they're written in a language that speaks directly to the challenges we face in chip design. With that caveat, here's a list of his latest nuggets:

• Rumors on Synfora, Forte, CatapultC, AutoESL, CoWare, Calypto, EVE. This doesn't read like EDA vendor spin, but rather some provocative EDA-insider scoop on M&A in the ESL space.
• A follow up first evaluation of Atoptech's new Apogee floorplanner
• Another production user on NextOp's BugScope assertion synthesis
• Some hands-on user experiences with HLS and AutoESL's AutoPilot
• Getting 100X scan compression with Talus Design and Mentor Tessent
• Cadence Virtuoso and Solido for variation-aware custom design. (clearly labeled as a white paper)
• Whitepaper on IC Manage unifying bug tracking & design management. (clearly labeled as a white paper)

2010 IEEE Medal of Honor Winner: Andrew J. Viterbi

Interesting profile of one of the giants of modern day technology, who's contributions we use and design with every day: IEEE Spectrum: 2010 Medal of Honor Winner: Andrew J. Viterbi.

At What Price Growth?

The blogosphere is afire with commentary on Cadence's acquisition of Denali, including

• Cadence to Acquire Denali: The Facts | Gabe on EDA
• Cadence to Acquire Denali: The Analysis | Gabe on EDA
• Cadence tries to avoid the Tality trap | Chris Edwards

Though I'm not a financial analyst, I do have reasonable familiarity with the stock market. And, being the thrifty guy that I am, I'm having trouble to justify Cadence's valuation of Denali. Pulling a quote from Gabe's analysis post, Denali had trailing twelve-month revenues of $43 million, implying a 6.3x EV/sales. Priced at over 6X Sales! For a company that's been around a number of years, and while it has a healthy business, is not forecast for hyper-growth? How do companies justify such valuations? (I'm asking sincerely--perhaps there's an analysis angle that makes this look like a good bet.)

The more I read, the more I scratch my head about whether this is a good venture for Cadence. Gotta give them credit for trying something outside the EDA product box, though. It seems they are gunning for Synopsys DesignWare IP business, and using Denali to give themselves a jump start.

Caveat: I haven't read Cadence's "EDA360 Manifesto", so I may not fully appreciate the cleverness of their overall strategy.

Will Cadence Take Away the Punch Bowl?

Big news in the world of EDA business this week, with Cadence to buy Denali for $315 million.

Though as an implementation guy, I don't use Denali products, the first things that sprang to mind are:

• $315 million is a lot of money! I think it must be one of the top 10 EDA acquisitions by price, if not top five. Anyone have list of the top acquisitions in EDA? It'd be fascinating to review the list and how those deals turned out.

  Off the top of my head guess list of bigger deals: CCT (Cadence), Ambit (Cadence), Avant! (Synopsys). Maybe ViewLogic (Synopsys), Verisity (Cadence).

• Cadence has been ambivalent or downright antagonistic toward the Design Automation Conference (DAC) in the past few years. Denali, on the other hand, is one of DAC's biggest boosters, and throws the party to attend in all of DAC. It will be tragic if Cadence clamps down on the festivities.

On a more somber note, let's hope that Cadence is able to preserve the technology and brain trust that was able to make Denali a well-established mid-level EDA vendor. Cadence has had mixed success in managing acquisitions, with some apparently not paying off (Ambit) and others holding up well (Verplex).

SCDsource & EDA technologies to watch out for at DAC 2010

The EDA/Semiconductor web site SCDsource is going away on May 7, but if you click now, you can read their preview of EDA technologies to watch out for at DAC 2010.

In the interest of preserving history, I'll list their picks here.

• Forte Cynthesizer
• Mentor Catapult C
• Wind River/Cadence Simics/Incisive Integration (Why does Cadence always have the most cumbersome product names? They must name them by committee, and everyone gets to add a word!)
• Oasys RealTime Designer
• Jasper DA JasperGold
• OneSpin Solutions 360 MV
• Magma Tekton
• Silicon Frontline F3D and R3D
• Sigrity PowerDC Thermal

iPad A4 == Intrinsity?

Wow, here's a flash, maybe Apple didn't design the "A4" brain of their iPad tablet after all: IEEE Spectrum: Evidence for Intrinsity in the iPad.

I always thought it curious that Apple supposedly pulled off such an ambitious chip with their first major in-house development. Pundits assumed that it was done with the help of Apple's P.A. Semi acquisition, but P.A. Semi had been focusing on the "Power" architecture, not ARM.

Old but Not Dead Languages

How can it possibly be that in this survey of programming language popularity, the C programming language is back at number 1 position?

I love technology history more than the average person, but I am dumb-founded that with all the software engineering development, object-oriented design, and graphical user interface work that's happened over the decades, we are relying on a language designed before many practicing engineers were born! (People may complain about Verilog HDL's crustiness, but it's "only" 25 years old.)

Though software engineering is not my principal occupation, I do enjoy programming and languages. I know "C" well enough to quickly shoot myself in the foot, but think Java is a far more elegant language. It's sort of like I've heard that Python is a better scripting language, but everyone still uses Perl.

Anyone have explanations for why "C" remains so popular? Isn't this a significant reason why computers have so many security holes? When you hear about "buffer overrun" and "malicious code execution", think "C" pointers! I can see using "C" for embedded systems if resources are very limited, but otherwise, I'm truly surprised by this survey.

SNUG's Happy Birthday

Early this month the Synopsys Users' Group conference was held in Santa Clara, California. It was a special SNUG, as it was the 20th anniversary. That's an eternity in EDA.

The conference featured record attendance (over 2,100) and a good balance of user papers on verification, implementation, signoff, and low-power design.

• Art de Geus' keynote. It's the much-anticipated "state of Synopsys" (and EDA, the semiconductor industry, and world economy).
• Award-winning papers. Congratulations to the everyone who presented a paper.
• Press Release. Includes list of awarded papers.

Automation End Game?

Thanks to EDA vendors for making hard to use and even harder to interoperate tools. I mean, what would happen to engineers if the tools were easy to use?

Engineers chime in on the A4

Or, as the VentureBeat columnist wryly put it, Apple’s A4 chip: Engineers correct stupid journalist. Some of the speculation is very plausible, and I found the anonymous quotes the most interesting of all, suggesting as reason for Apple to design their own chip

• efficiency (exactly what they need, no more)
• business/schedule
• cost: a big upfront development cost to slash the per-part cost

Some additional details, not quite as juicy, follow in How Apple’s A4 chip lets iPad run cooler, save battery life. I was most surprised at the claim from "a very trusted source" that PA Semi didn’t do the A4. It was the existing VLSI team. Could it be true? All other speculation I read was that this was the fruit of Apple's investment in PA Semi. (Although PA Semi was working on PowerPC designs, and the iPad's A4 is almost surely ARM-based.)

Scooping the MSM on A4

(That's the Mainstream Media, for those of you with lives outside of the blogosphere.) Today in the New York Times, there's a perspective on the iPad A4 chip, In the iPad, Apple Is Betting on Its Own Microchip. The analysts interviewed in the article are similarly nonplussed by Apple's chip design strategy. But the Times did snag a nice picture of the chip:

Update: Business Week's A4 story. I was never expecting Intel to be a contender for the iPad design win. And how does an analyst already estimate the cost of the A4 chip and the iPad's bill of materials? Has anyone got their hands on one outside of Apple?

Steve Jobs, Chip Wizard

This week saw a big day in the world of Technology, with Apple announcing the incredibly hyped iPad tablet. The Mercury News and The Wall Street Journal, among many others, each devoted a few pages to coverage.

As good tech consumers, we all have our opinions about the features, price point, and odds of it changing the world. Steve Jobs called it "magical". (Fake Steve says he uses neuro-linguistic programming.)

But I digress. What's the significance for chip-design engineers? Though we won't have the details from a full teardown for another couple of months, Apple did announce that they've designed the central chip in the iPad, dubbing it the "A4". Early coverage of A4 includes

• Eagerly awaiting info on Apple's A4 chip for the iPad and how its PA Semi buy fits in ... - Now Hear This! - Blog on EDN - 1750000175
• Apple-Designed Chip Marks Strategy Shift

It's intriguing that Apple has consciously decided to build an advanced chip design organization, since they are a consumer electronics company. There are comparable alternatives for single-chip mobile device computers, including the Qualcomm Snapdragon and NVIDIA Tegra. What's Apple's angle in doing it themselves? Is it just their obsessive need for secrecy? Or will they somehow integrate differentiating functions that justify the large investment and risk of running a chip design operation? It flies against the industry trend (which PC manufacturer designs its own chips?), but let's see how this plays out. I'm not foolish enough to dismiss Steve Jobs' ability to Think Different.