Thursday, July 28, 2005

CDNLive! Conference

Cadence's answer to SNUG, the Synopsys User Group, is CDNLive! The schedule looks pretty good -- interesting and relevant. Looks like they also managed to get customers to present their advanced product experiences rather than relying on their own marketing pitches. If you're interested, early registration discount ends on August 12.

Wednesday, July 27, 2005

Improving yield in RTL-to-GDSII flows

I'm very curious about how front-end or RTL design can influence manufacturability or yield in a Standard Cell flow. I don't see the connection.

Improving yield in RTL-to-GDSII flows sounds like it would explain it all for me, but the connection to RTL design still seems to be missing. I see where synthesis might be able to select cells out of a "high yield" library (if such a beast existed), and certainly there are things to do during routing, such as adding redundant vias. But this is all physical design. Is the logic designer off the hook?

A Plethora of White Papers

Magma Design Automation, Inc. - White Papers lists a number of relevant and well-written White Papers, including non Magma-specific topics such as
  • Signal Integrity
  • Visualizing the behavior of Logic Synthesis algorithms

Some of the other papers are more oriented to Magma tool capabilities, but because their tool suite is modern and novel, they should be informative as well.

Wednesday, July 20, 2005

Designing for New Dimensions

This is very "researchy" stuff, but it could dramatically reduce interconnect length, much better even than "X Architecture". Designing for New Dimensions refers to the third dimension, previously unexploited in IC design. And a picture is worth 10^3 words:

Retrospective on DAC and EDA

Ditchin' DAC is a long-time DAC veteran's take on the evolution of the Design Automation Conference, from the beginnings as a clearinghouse of Corporate CAD developments, through the booming tradeshow of the 1990s, to now, where some question whether DAC is worth the cost and time. I'm on the fence. I'd go to DAC if it were local, but usually can't justify the time and expense to travel there. DAC hasn't been in the Bay Area in several years, although we probably have the greatest number of industry customers.

Monday, July 18, 2005

Tenzing Norgay Interoperability Achievement Award?

This has long struck me as the most incongruous award in our industry: ARM Recipient of Synopsys Fifth Annual Tenzing Norgay Interoperability Achievement Award. Yes, I know who Tenzing Norgay is, but the connection to EDA??? It reminds me so much of Apple using pictures of Einstein and Gandhi to promote their products.
Interoperability plays a key role in elevating designers to a higher level of productivity, just as Tenzing Norgay's efforts facilitated the first ascent to the top of Mount Everest, said Rich Goldman, vice president, Strategic Alliance at Synopsys.

Ah, it all makes sense now. ;-)

Hot Chips' Conference Preview - Hot Chips' message: It's the bandwidth gives a head-up as to the themes to be presented at the August Hot Chips conference. The top problems designers face are
  1. Managing power
  2. Managing the memory bandwidth bottleneck
Here for the foreseeable future is a world of parallelism, of increasingly application-directed architectures and of an unending struggle for memory bandwidth rather than Mips.

Monday, July 11, 2005

The RISC that did not pay off - The RISC that did not pay off points out that while Reduced Instruction Set Computing was the rage starting in the 1980s, the reasons for its appeal are no longer dominant. Memory bandwidth has become a huge bottleneck, which wasn't the case when RISC was on the ascent.

LSI Logic RapidChip & Structured ASIC

I've always been intrigued by initiatives to bring down the ever-increasing cost of nanometer-scale IC design. While mask sets can cost more than $1M, I fondly remember the days of Gate Array vendors' ability to turn prootypes in less than a week! LSI Logic's Leverage reads like a PR piece written by LSI Logic about RapidChip, their Structured ASIC product. While intrigued, I want to understand about these technologies:
  1. How do they know what IP to diffuse onto the base layers? How do you reconcile if one customer wants N Serdes macros, and another wants M megabits of RAM?
  2. Who is really using Structured ASIC? How real is it, and for what applications?

Thursday, July 07, 2005

Sequence CoolPower: SoC Power and Voltage Drop Optimization

Sequence CoolPower First with Comprehensive SoC Power and Voltage Drop Optimization; New Automated MTCMOS Power Gating Slashes Leakage up to 100X, CoolPower Reduces Voltage Drop Significantly with No Timing/SI Penalty is in the running for the longest-titled Press Release! The march toward low-power methodologies continues. While Vth optimization is localized and has few side effects, emerging techniques such as Power Gating have implications for design, verification, and implementation methdologies. I don't know how cleanly this works yet. Sequence is announcing a product to support this, and I imagine the big EDA players will address this as well. BTW, Sequence neglected to define MTCMOS. It stands for Multi-Threshold CMOS. The idea is that the regular functional transistors are low-threshold (high-speed, high leakage), but the power to these transistors is gated by a high-threshold transistor during non-operation or "sleep".
Discovering Multi-Core: Extending the Benefits of Moore's Law is a well-written laymen's description of the challenges to Moore's Law as we face physical limits in scaling chips.
  • The argument for "scaling out" is similar to NVIDIA's SLI strategy, which links two GPUs to work in parallel on graphics rendering.

Friday, July 01, 2005

Reflections on DAC

Reflections on DAC by Gabe Moretti is an good overview of this year's Design Automation Conference. Other than his tedious attempt to define a new taxonomy for the EDA market, I enjoyed his observations about the show and analysis of the big EDA vendors.

Sony May Lose Up to $1.18 Billion on PlayStation 3 – Merrill Lynch

Sony May Lose Up to $1.18 Billion on PlayStation 3 – Merrill Lynch is an interesting analysis of the economics of game console hardware. ... estimates that the machine’s main components – namely its Cell chip, NVIDIA RSX graphics processor and BD-ROM drive – will cost about $101 each. Oh well, they will sell a lot of $50 game CDs to recoup the hardware cost!