Great summary by Gabe of an IBM talk on the big technical challenges to scaling CMOS further. Some of the points that caught my eye:
- silicon CMOS is viable for at least 10 years down to around 22 nm range
- Power & leakage management are essential
- next generations of CMOS will change to metal gate and high k dielectric materials. Hey, doesn't the "M" in CMOS stand for Metal, anyway? Why did we start using polysilicon gates and still call it CMOS? Should be CPOS!
- Yield variability is addressed in three categories: lot-lot, regional systematic, and local systematic. ... The real challenge is the local random variations. Because of the atomic scale of the devices, all effects are a function of small number statistics.