The article acknowledges that the systemC flow has holes. It was interesting to read that people are translating RTL to SystemC. What do you call synthesis in reverse? Abstraction? It sort of makes sense if you get a huge simulation speedup, but robust synthesis and verification from SystemC to RTL would help productivity much more. That is still out in the future for the general case.
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Verification from SystemC to RTL?? I make my living off that - check out SLEC System
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