Charter for a Corporate CAD Group

I discovered another EDA-related blog, Cool Verification. Cool Verification: Creating Corporate Standards? Beware... is an excellent post outlining the considerations in creating and managing a "Corporate CAD" department.

I've taken this group's mission for granted, but my company didn't even have such a department four years ago, even as it was cranking out huge industry-leading chips. What finally pushed us to create a central group was the proliferation of derivative chips and especially the diverse chips being designed by new business units. It no longer made sense to have a few "designers with a tool fetish" responsible for creating and maintaining all the flows. Hence, a CAD department was born. The referenced post touches upon the dynamics of trying to please all groups in the face of different requirements and priorities.

EDA Confessions, Part I

After my prescient DAC trip report, I've been thinking of a couple of times in my career when I've really missed the boat on EDA companies. I have a couple of examples that I can't forget. I'll write about them one at a time. Confession is good for the soul. ;-) The first is a company that I ignored, yet in retrospect could have done a great jobs for us.

The Time

Late 1990s

Product Type

Floorplanner

The Company

Silicon Perspective (SPC)

The Problem

My company was working with Synopsys on "Chip Architect" and "Floorplan Manager" to close timing on "deep submicron" designs. These were around 0.35 micron, IIRC. I never used Chip Architect, but my colleagues were beta testing and helping to debug it. I spent a lot of time with Floorplan Manager; it was pretty inefficient to back-annotate tons of layout data onto Design Compiler, and for DC to optimize designs in a way both effective and feasible for physical design. We were struggling to close timing on the design.

The pitch

An SPC Sales guy kept calling me, asking us to evaluate FE. He made extraordinary claims about its performance, capacity, and quality of results. He wanted us to try it on a multimedia design one of our groups was working on.

What I did

I couldn't believe that this little startup could deliver such amazing results that Synopsys and Cadence couldn't! Clearly, he was just making wild claims to get our attention. So, I never did bring him in for an evaluation.

What happened

Our design project took so long and it was eventually cancelled. And I ended up leaving the company around the same time. Later, SPC was acquired by Cadence for a large sum and today is the foundation and namesake of "Encounter", their whole family of Digital IC implementation products!

Lesson learned

Don't dismiss startups lightly! Consider them skeptically, but give them a chance if their story seems plausible.

Graphics Beginners' Guide | Tom's Hardware

Graphics Beginners' Guide | Tom's Hardware is a great introduction for understanding (and purchasing :-) today's graphics cards.

It's a series of three articles, all of which are accessible from this page.

After the AMD / ATI merger: Will Nvidia GeForce still compete with ATI Radeon?

After the AMD / ATI merger: Will Nvidia GeForce still compete with ATI Radeon? | TG Daily is the best in-depth analysis I've seen of the implications of the AMD acquiring ATI. It lays out a number of scenarios, but the end game is far from clear.

2006 DAC Report

Introduction

The "hot" areas of EDA these days are Electronic System Level (ESL) and Design For Manufacturing (DFM). Indeed, there were numerous companies offering things such as SystemC design or yield-aware layout tools.

I attended DAC for one day, Wednesday. I focused on low-power and variation-aware tools, and compiled a list of companies participating in these areas. I had time to see about half the companies I identified. Below is a short summary of my impression of those companies.

Companies that Impressed

• Azuro. Low-power clock design. They optimize clock gating and physical clock tree for low power. They claim 15-25% less power than using today's tools. This is a niche tool that is worth looking at. The most impressive thing I saw at DAC was their clock tree analysis/visualization tool. At a glance, the design can visualize the structure and quality of the clock tree. It's better than any analysis I've seen before.

• Altos. Library characterization, including statistical effects. Their characterization system, Liberate, includes their own very fast SPICE-like engine. They claim ~10X faster than today's tools. They can generate .lib and also the latest CCS and ECSM models. They appear to have a solid grasp of what's needed for statistical characterization, and their high performance will be very welcome for that. They're working to support SSTA from Extreme DA. The founders are from CadMOS (SI tool acquired by Cadence) and seem sharp. They recently published an article in EE Times. [Note: Magma just announced an upgrade to their characterization system.]

• Proficient. Low-power design. Intriguing. It seems like a pretty small company.

• Prolific. Post-layout power & timing improvement. Their tool may be useful and the approach is sensible and simple (bolting onto PrimeTime). Designers could do something like this themselves, but if their tool is reasonably priced and effective, it may be worth it.

• TSMC. They conducted a series of advanced methodology presentations. It is impressive how much they've thought through the whole methodology and worked with EDA vendors on their "Reference Flow 7.0".

Companies that Didn't Impress

Censored! I'm don't yet have John Cooley's nerve to dis companies in public. In my case, it wouldn't really be fair to opine on them after a half-hour presentation or demo, anyway.

Other Notes

• "Power Forward Initiative" lunch hosted by Cadence. This is a consortium initiated by Cadence to develop a standard "CPF" Common Power Format description of low-power design intent. CPF would drive implementation, checking and analysis tools. Something like SDC is for timing. This may bear fruit in a couple of years, but of concern is that Synopsys is not on board. Will it be another political fight like CCS vs. ECSM? [Yes, the politics have already started with a Synopsys counter-proposal.]
• Coincident with DAC, Synopsys announced enhancements to PrimeTime and Star-RCXT with statistical capabilities.

Best Freebie

There didn't appear to be major schwag as I remember from years ago. I remember when you could always count on Viewlogic for a bat or a hockey stick, or Altera for a soccer ball. However, one gift at this year's DAC impressed me. It was the hand-held fan from Bluespec. It appears to be your standard simple battery-powered fan. However, there are LEDs embedded in the fan blades, and when you turn it on and the fan spins, the lights spell out promotional messages for Bluespec. Pretty "cool"!

Other Coverage

• EE Times DAC Coverage
• EDN DAC Daily Report
• Gary Smith's What to see at DAC List
• John Cooley's Cheesy Must See List for DAC 2006

Cooley's Must See List for DAC 2006

It's unfortunate I didn't see this before going to DAC, but EDA Gadfly John Cooley posted an extensive Must See List for DAC 2006.

John's list is quite long, spread out over 24 categories. Rather than being very discriminating, it's more of a concise summary of all that's new and significant at DAC.

Companies Common to Cooley and Busco Lists

• Altos - Statistical timing characterization
• Apache - IR drop analysis.
• Athena - simultaneous timing closure (post-route)
• Azuro - low power clock implementation
• ChipVision - Low-power ESL design
• Extreme DA - Statistical STA
• Forte - SystemC synthesis
• Magma - Talus implementation system, Blast Fusion design closure
• Prolific - post P&R timing optimization
• Sierra DA - physical synthesis & routing.
• Zenasis - custom cell generation for timing optimization

Companies Common to Cooley, Smith, and Busco Lists

• Apache
• Forte Design Systems
• Magma DA
• Sierra DA

Gary Smith's Must-See List

Coincidentally, just after posting my DAC must-see list, I see the list of veteran EDA industry observer Gary Smith. His list is broader than mine with a good dose of "ESL" and "SVP" vendors: EETimes.com - Imperas tops analyst Smith's watch list

Looking for intersections, we both mentioned the following vendors:

• Apache
• Forte Design Systems
• Magma DA
• Sierra DA
• Proficient Design

It appears that I don't share Gary's enthusiasm for ESL, and he really doesn't share my enthusiasm for "statistical" or "variation" analysis.

DAC is Here!

EE Times is doing a nice job of covering the Design Automation Conference, which started yesterday in San Francisco. Road to DAC: Complete Conference Coverage has lots of articles and even a set of webcasts that includes an interview with Joe Costello, former Cadence CEO and EDA celebrity.

Thought I'd post the list of companies that I'm interested to visit. It is far from a comprehensive list, but these are companies mostly in the "design implementation" space that piqued my interest based on what I've read.

• Altos - Statistical timing characterization
• Apache - IR drop analysis.
• Athena - simultaneous timing closure (post-route)
• Azuro - low power clock implementation
• ChipVision - Low-power ESL design
• Extreme DA - Statistical STA
• Forte - SystemC synthesis
• Magma - Talus implementation system, Blast Fusion design closure
• Proficient - Low power design
• Prolific - post P&R timing optimization
• Sierra DA - physical synthesis & routing.
• TSMC - Reference Flow 7.0
• Zenasis - custom cell generation for timing optimization

EDA Players Detail Involvement in TSMC Reference Flow

EDA Players Detail Involvement in TSMC Reference Flow - 7/18/2006 - Electronic News details which EDA vendors are providing which tools and technologies for TSMC's recently updated "reference flow".

With respect to statistical STA, an area of interest to me, the article sites support from Cadence and Magma, but not Synopsys. That's funny, I don't think of Cadence as a player in the timing space. They don't even really have an STA tool, do they? I thought all their customers sign off on PrimeTime.

TSMC Flow Adds Statistical STA

TSMC (Waferzilla?) has announced the latest additions to their Reference Flow, version 7.0. The two main additions are Statistical STA and more Power Management features.

Interesting that the Statistical STA flow supports vendors Magma and Synopsys. Magma has been promoting their Quartz STA tool. Has Synopsys announced a Statistical STA tool? I don't recall seeing it.

And, what about library support? How will this be done? I haven't seen any standards offered for representing variation in Liberty format, for example.

Overall, this announcement is a hopeful sign, but I wonder how real it is, or when we might actually see a working flow.

Statistical Characterization and STA Primer

Cell model creation for statistical timing analysis is a great primer on Statistical Static Timing Analysis (SSTA). It's written from the viewpoint of the challenges facing statistical library characterization. After reading this article, I wonder how we're *ever* going to have a complete set of SSTA-characterized libraries. Fortunately, the EDA startup Altos, which is where one of the authors works, has a solution under development. Unaddressed by this article is how such characterization will be represented for all the vendors' STA tools. As of now, there is no .lib "Liberty" standard for statistical modeling. We've got a long ways to go!

Metcalfe's Law is Wrong

IEEE Spectrum: Metcalfe's Law is Wrong gives in-depth analysis to one of those laws that people accepted uncritically.

I don't know what analysis Metcalfe's original "law" was based upon, but it doesn't seem as robust as Moore's law. The paper referenced here goes on to hypothesize what the law regarding the value of networks should have been. It dovetails nicely with another concept, the "long tail", that comes up when discussing e-commerce, blogs, and many other phenomena.

DAC's 44 New Exhibitors

Do you know much about these new EDA companies? 43rd Design Automation Conference to Feature 44 New Exhibitors They're news to me. Which ones will capture enough interest to thrive?

Power Primer

Power Management DesignLine | Low Power CMOS Circuit Design is an excellent survey of CMOS power consumption along with the most common techniques to reduce power.

This article is a good quick reference -- why, these questions might even come up in an interview! ;-)

Hot Summer for CPU Companies

Hot Summer for CPU Companies is a nice summary of the recent CPU wars, and how Intel Israel's designs may yet save the bacon of "Chipzilla".

I wonder what tricks they're using for power-efficient design?

Lies, Damn Lies, and Engineering Manpower

Heard the One About the 600,000 Chinese Engineers? is very interesting for how a set of poorly-vetted data can take on a life of their own.

I've heard the IEEE-USA referring to such numbers, too. I think their interest is a combination of wanting to strengthen American competitiveness, but also to ensure increased funding for engineering education and research. In other words, self-serving for the greater good!

Cadence Powers Forward

I wasn't sure to make of Cadence's announced Power Forward Initiative. This is such a nascent field, do we know what to standardize?

But then I could think of some design practices that would be very good to have a standard way to describe and verify, such as what voltage and power domains various parts of the design should be connected to, what is the design convention for isolation and level shifting, etc.

This could be a useful standard. Let's hope it doesn't degrade into another Cadence vs. Synopsys "we have two standards so we have no standard" like ECSM and CCS libraries!

Semi Business is too good? Allocation, here we come!

The headline EETimes.com - TSMC puts customers on allocation certainly caught my eye and made me think of the good ol' days.

But reading the fine print, this is only for older geometries, i.e., 0.18 and 0.25 micron. Even though there ought to be lots of "second-tier" fabs with capacity, especially in China, the article explains that it's difficult to port mixed-signal design from one process to another. Once you go to production with a particular foundry on these types of "touchy" designs, you are in bed with that foundry for a long time!

TSMC DFM format empowers fabless design

Good news! Fabless semiconductor vendors (e.g., NVDA, BRCM, etc.) won't be up a creek in getting yields at 65nm and below: EETimes.com - TSMC DFM format empowers fabless design

If this works as advertised, this collaboration will enable TSMC + EDA vendors to work like an Integrated Device Manufacturer (IDM), and not suffer from walls and insufficient information sharing.

I'm looking forward to the TSMC Technology Symposium, which is always good for seeing how the foundry world operates, and what interesting issues they address that we seldom hear about in the "front-end" design world.

Startups to watch

This is an intriguing list of startups, though the selection criteria is rather mysterious. Reviewing it gives you a feel for what's coming and what's hot in our industry. I spotted a few EDA companies, several in the "DFM" space and at least one related to "ESL" design.

"editors have selected companies based on a mix of criteria including: technology, intended market, maturity, financial position and investment profile.

Startups on the Silicon 60 list include companies involved in semiconductor chips, memory, fab equipment, packaging, foundry, materials, MEMS and EDA software that made an impression on EE Times editors. They are emerging companies to watch for a wide variety of reasons.

EETimes.com - EE Times updates list of emerging startups