Good news! Fabless semiconductor vendors (e.g., NVDA, BRCM, etc.) won't be up a creek in getting yields at 65nm and below: EETimes.com - TSMC DFM format empowers fabless design
If this works as advertised, this collaboration will enable TSMC + EDA vendors to work like an Integrated Device Manufacturer (IDM), and not suffer from walls and insufficient information sharing.
I'm looking forward to the TSMC Technology Symposium, which is always good for seeing how the foundry world operates, and what interesting issues they address that we seldom hear about in the "front-end" design world.