Spying DAC from Afar

Vendors to See, Vendors to Overlook?

I don't mean to become a "riff on John Cooley" blog, but it turns out he's pumped out some provocative missives leading up to next week's Design Automation Conference (DAC). I was about to write a post on "what I'd see at DAC", when along came Cooley's Cheesy Must See List for DAC 2010. Before we review his list, let me offer my own list of interesting products and technologies. This won't be as expansive as John's list, since I spend most of my time using or considering implementation tools.

Intriguing Products

• Magma Tekton. The tool is targeted to be a better, more modern PrimeTime. Usable as a drop-in replacement, with claimed significant speed and capacity advantages, and attractive added features like SPICE integration and MCMM analysis.
• Oasys RealTime Designer. I wrote about Oasys last year, when they came out of stealth mode. Now, they're rolling out customer testimonials from Xilinx and Juniper Networks. Harry the ASIC Guy, who's been around the EDA industry, has some interesting theories about where Oasys may find business.

Interesting Technologies

• Silicon IP. This is the most sure-fire way to develop 45nm and 28nm chips in an economical way. But do you want to become the general contractor for a dozen IP vendors? You may not have to, with consolidation such as Cadence acquiring Denali and Synopsys acquiring Virage Logic.
• ESL. It's always seemed like a logical step up the abstraction ladder to rise above RTL. There's lots of M&A activity here, with Synopsys and others gobbling up ESL synthesis companies.
• Variation-Aware Analysis. Will SSTA ever be ready for prime time? It's been the Next Big Thing in EDA for a few years, but there is little PT-VX talk at SNUG, and most of the STA startups are focusing on beating PrimeTime at traditional corner analysis rather than SSTA.
• Asynchronous Design. I'm intrigued by not having to synchronize a clock across a chip, and hardening cross-chip interfaces to variation. But I've seen little in the way of IP or automation to realize such unconventional design techniques. Are there any vendors out there? Who are the academic research leaders?

The Cheesy List

I do admire John Cooley's list for its breadth. For the most part, I think he hits the major players in each area and captures the talking points that they're featuring for this DAC.

With one notable exception. Did you notice that his list doesn't feature a certain EDA company that's hard to overlook? That's right, Synopsys. He doesn't feature one Synopsys product in his list! That's a curious oversight to me. While I do think that much of EDA innovation comes from smaller companies, Synopsys does hold its own in innovation compared to Cadence or Mentor, but those companies did have featured products in John's list. Are John and Synopsys having a spat, or is he getting ready to roll out his exclusive must-see Synopsys list?

Pre-DAC EDA Gossip and "User Evaluations"

John Cooley is the original user's voice in EDA, and his DeepChip web site and mailing list continue to have the biggest following. I used to think of John as "the Michael Moore of EDA" -- a rabble-rouser, confronting the dominant companies and their executives, and sticking up for the little guy.

He still has that image, but I've come to realize that the in-depth tool evaluations that he posts aren't always the innocent sharings of chip engineers that they appear to be. There's definitely an element of the EDA vendors' PR machines in some write-ups. That's OK, as long as you take them as such. If these articles are really EDA vendor white papers or press releases, at least they're written in a language that speaks directly to the challenges we face in chip design. With that caveat, here's a list of his latest nuggets:

• Rumors on Synfora, Forte, CatapultC, AutoESL, CoWare, Calypto, EVE. This doesn't read like EDA vendor spin, but rather some provocative EDA-insider scoop on M&A in the ESL space.
• A follow up first evaluation of Atoptech's new Apogee floorplanner
• Another production user on NextOp's BugScope assertion synthesis
• Some hands-on user experiences with HLS and AutoESL's AutoPilot
• Getting 100X scan compression with Talus Design and Mentor Tessent
• Cadence Virtuoso and Solido for variation-aware custom design. (clearly labeled as a white paper)
• Whitepaper on IC Manage unifying bug tracking & design management. (clearly labeled as a white paper)