Constructing the next transistor , in EE Times, is a superb article describing the technical challenges to building useful transistors below 65nm. It covers the physical and materials challenges that are arising, and how the solution to one problem (e.g., low leakage power) may aggravate another (high performance).
I'd love to have seen this illustrated with some pictures -- I wonder if the print edition has that? In any case, if you're a semiconductor engineer or scientist, you'll find this article worthwhile.
Why, it even makes me want to dust off my semiconductor textbooks to remember what's really going on inside a MOS transistor!
2 comments:
Nice find John!!
The technologies driving high performance and low power were always at odds with each other. For example, higher frequency meant higher dynamic power dissipation, but lowering the frequency meant loss of performance.
We used to tackle this by clever usage of voltage "island" technology - isolating some areas by using clock gating, switching off entire regions, etc.,
But at sub-65 nm, leakage power is apparently so great ( I had no idea about these new kinds of leakages!!), that all the smart low-power techniques are no longer so useful.
Hmm, wonder what new design techniques will have to be invented, or whether this is a fab-end thing only.
Hi Sandeep,
Yes, power dissipation is becoming a big problem, and leakage power can be comparable or larger than dynamic power! I too wonder what can be done from the design (as opposed to fab) end.
The "next big thing" that I've heard about is Power Gating, where the design would include power gating transistors inline with the power rails. This would allow you to completely pinch off leakage power when you're not using a block of logic.
There are other techniques, such as manipulating back-bias voltage. I need to crack open the textbooks to review that one.
John
Post a Comment