Interesting that the authors are from Cadence. I didn't know they were big players in the STA arena. I know they have an "Encounter" timing system, but I'm not familiar with how advanced or accepted it is.
The article reinforces my view that statistical STA is "not ready for PrimeTime". That pun is not a slam against Synopsys! I mean that there needs to be a lot more support from the foundries and understanding by the design community before there's much adoption of SSTA for production chip timing.
Another good article, which was just published and is written by Extreme DA's founder, is Statistical static timing analysis: A view from the future.
3 comments:
IBM claims that they have taped out atleast 1500 chips using EinsTimer (their internal SSTA tool).
Dunno if it is all marketing hype or real.
I think that either the author or IBM does a disservice by confusing IBM's workhorse STA tool, "EinsTimer", with their
enhancements for statistical STA, which may be called "EinStat" (sp?).
EinsTimer may easily have 1500 tape-outs, since it's used by IBM Microelectronics for their ASIC business.
But I think that statistical tool
would have been used for a very
small number of those designs.
Good article and blog, John! I will add you to my blogroll.
Cheers
http://opensemi.blogspot.com
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