Tuesday, March 07, 2006

SystemVerilog, a better RTL

I'm looking forward to being able to use SystemVerilog for Design (synthesis). Looks like this effort is picking up according to EETimes.com - Vendors warm to SystemVerilog

I haven't done a thorough survey of the language, but a few of the things that will help Design/Synthesis are:

  • Interfaces (objects that define ports (and even protocols) between designs)
  • Explicit treatment of intent for case statements
  • Explicit treatment of intent for always blocks
I'm sure there are many more. I look forward to trying it.

Is Synopsys undermining synthesis standardization? Gee, they'd never do that. ;-) Looked at from the perspective of protecting their franchise, they have the most to lose from making designs portable. We've the same types of battles over library standardization (finally, Liberty) and a synthesis subset for Verilog HDL.

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