Thursday, June 30, 2005
EDA analyst Gabe Moretti has written an insightful analysis of offshoring and issues facing engineers in particular. Take a gander at Do we have a brain balance deficit?. I agree that H-1B workers are better for the US than offshore outsourcing! I also relate to his observations on why an engineering career isn't as attractive as medicine or law.
An interesting explanation inDelay of ATI R520 to boost Nvidia 4Q sales: the company is facing leakage issues, as it attempts to migrates its manufacturing to a 90nm process It is rare to see such a specific attribution of production problems! I wonder what techniques they are using and what's not working? Vth optimization? Power Gating? ...
Monday, June 27, 2005
Startups at DAC fielding interesting new products were covered in EETimes.com - Three tout more nimble physical design
- Magma's Quart-DRC high-performance distributed DRC.
- Apache PsiWinder critical-path and clock tree analysis tool that considers crosstalk and dynamic-power integrity effects.
- Sierra Pinnacle physical-synthesis tool to concurrently optimize timing, area, power and signal integrity across all operating modes and corners.
Wednesday, June 22, 2005
Monday, June 13, 2005
The X Architecture initiative, an early example of which is described in ATI, Cadence and TSMC Produce Industry's First Fabless X Architecture Chip, is based on a straightforward idea: rather than run all the wires on an IC horizontally and vertically (Manhattan routing), devote a couple of layers to routing diagonally at 45 and 135 degrees. It allows you to "cut the corner" and routing distances become shorter. I think the biggest challenges to making this work are on the manufacturing side, which is why there's been heavy involvement from foundries like TSMC and semiconductor equipment manufacturers. I first heard about the X Initiative when Simplex Solutions and Toshiba were working on it several years ago. Cadence acquired Simplex, and this technology is starting to be introduced commercially now. UPDATE: This article has more technical detail.
Friday, June 10, 2005
TSMC issued a press release to announce their Reference Flow 6.0. It emphasizes (1) low-power design, including building blocks for a "power gating" methodology, and (2) Design For Manufacturing. It's also interesting that TSMC's trend is to integrate more value-add rather than be a 100% pure manufacturer. For example, TSMC is offering their own libraries for standard cells, memories, and I/O. It may be that this is natural, given the increasing relationship between Design and Manufacturing. But it should also help their business margins as they add more value. UPDATE: EETimes.com - TSMC reference flow heralds 65-nm transition
Tuesday, June 07, 2005
ChipEstimate.com is a very interesting concept to help a chip management team "size up" a proposed IC. Based on high-level information about gate count and IP used, it comes up with a floorplan and, at an additional cost, will provide budget estimates for manufacturing the chip with various foundries' processes. I remember that eSilicon had a similar budgeter, though it was intended for designs to be done with eSilicon. This ChipEstimate.com appears to be a standalone estimation product.
Monday, June 06, 2005
I've been reading this paper, Design for Manufacturing: What Designers Need to Know About the Change in Yield Management, at lunchtime, and find it to be an excellent overview of all the "DFM" effects that you hear about. Antenna effects, need for metal fill, what's wrong with Copper, are all topics that are covered in an introductory way. Nice starter!
Friday, June 03, 2005
EETimes.com - IBM markets statistical timing analyzer announces IBM's (re-)entry into the commercial EDA market. "Statistical STA" is new and hot. It should allow for less pessimistic STA, which becomes a critical requirement around 65nm. If you guardband to assume that every parameter is 3-sigma worst case, that's an unrealistic situation. A Statistical STA tool would understand that what combination of variations would happen with 3-sigma probability. Magma plans to launch a tool, but I haven't seen Synopsys or Cadence announce anything. Another type of variation is "location-based correlation". I don't see that addressed by the IBM STA tool.
Thursday, June 02, 2005
Wednesday, June 01, 2005
E3: Game Console Wars and Booth Babes provides a very good overview and comparison of the next-generation gaming consoles. As for the ultimate winner, it's way to early to know. But the article does take Sony to task for showing too much "smoke and mirrors", whereas Microsoft is showing real development. You have to read all the way to the end to see the "Booth Babes", but they are in there! Nothing like any conference I've ever been sent to!