The author, Shankar Krishnamoorthy of Sierra Design Automation, describes the very typical timing analysis and design closure flow, where many different modes and PVT corners must be considered, yet closure tools only understand one or two of the scenarios.
The rigorous treatment of design variation, classified in a matrix of variablility "causes" vs. "effects", is the best treatment I've seen in a public article. (EDA vendors will show similar analyses when privately pitching their new variation-aware products.)
Surprisingly, the author does not conclude that "statistical" timing analysis, which is all the rage in the EDA community, is a panacea. He points out the difficulties of getting statistical characterization data for process, libraries, and interconnect. He also asserts that Hold time violations require analysis at whichever corner most aggravates a particular violation (calling for multi-corner analysis).
Very thought provoking! It will be interesting to see what products Sierra comes up with to address this growing IC design closure problem.
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