Old but Not Dead Languages

How can it possibly be that in this survey of programming language popularity, the C programming language is back at number 1 position?

I love technology history more than the average person, but I am dumb-founded that with all the software engineering development, object-oriented design, and graphical user interface work that's happened over the decades, we are relying on a language designed before many practicing engineers were born! (People may complain about Verilog HDL's crustiness, but it's "only" 25 years old.)

Though software engineering is not my principal occupation, I do enjoy programming and languages. I know "C" well enough to quickly shoot myself in the foot, but think Java is a far more elegant language. It's sort of like I've heard that Python is a better scripting language, but everyone still uses Perl.

Anyone have explanations for why "C" remains so popular? Isn't this a significant reason why computers have so many security holes? When you hear about "buffer overrun" and "malicious code execution", think "C" pointers! I can see using "C" for embedded systems if resources are very limited, but otherwise, I'm truly surprised by this survey.

SNUG's Happy Birthday

Early this month the Synopsys Users' Group conference was held in Santa Clara, California. It was a special SNUG, as it was the 20th anniversary. That's an eternity in EDA.

The conference featured record attendance (over 2,100) and a good balance of user papers on verification, implementation, signoff, and low-power design.

• Art de Geus' keynote. It's the much-anticipated "state of Synopsys" (and EDA, the semiconductor industry, and world economy).
• Award-winning papers. Congratulations to the everyone who presented a paper.
• Press Release. Includes list of awarded papers.

Automation End Game?

Thanks to EDA vendors for making hard to use and even harder to interoperate tools. I mean, what would happen to engineers if the tools were easy to use?

Engineers chime in on the A4

Or, as the VentureBeat columnist wryly put it, Apple’s A4 chip: Engineers correct stupid journalist. Some of the speculation is very plausible, and I found the anonymous quotes the most interesting of all, suggesting as reason for Apple to design their own chip

• efficiency (exactly what they need, no more)
• business/schedule
• cost: a big upfront development cost to slash the per-part cost

Some additional details, not quite as juicy, follow in How Apple’s A4 chip lets iPad run cooler, save battery life. I was most surprised at the claim from "a very trusted source" that PA Semi didn’t do the A4. It was the existing VLSI team. Could it be true? All other speculation I read was that this was the fruit of Apple's investment in PA Semi. (Although PA Semi was working on PowerPC designs, and the iPad's A4 is almost surely ARM-based.)

Scooping the MSM on A4

(That's the Mainstream Media, for those of you with lives outside of the blogosphere.) Today in the New York Times, there's a perspective on the iPad A4 chip, In the iPad, Apple Is Betting on Its Own Microchip. The analysts interviewed in the article are similarly nonplussed by Apple's chip design strategy. But the Times did snag a nice picture of the chip:

Update: Business Week's A4 story. I was never expecting Intel to be a contender for the iPad design win. And how does an analyst already estimate the cost of the A4 chip and the iPad's bill of materials? Has anyone got their hands on one outside of Apple?

Steve Jobs, Chip Wizard

This week saw a big day in the world of Technology, with Apple announcing the incredibly hyped iPad tablet. The Mercury News and The Wall Street Journal, among many others, each devoted a few pages to coverage.

As good tech consumers, we all have our opinions about the features, price point, and odds of it changing the world. Steve Jobs called it "magical". (Fake Steve says he uses neuro-linguistic programming.)

But I digress. What's the significance for chip-design engineers? Though we won't have the details from a full teardown for another couple of months, Apple did announce that they've designed the central chip in the iPad, dubbing it the "A4". Early coverage of A4 includes

• Eagerly awaiting info on Apple's A4 chip for the iPad and how its PA Semi buy fits in ... - Now Hear This! - Blog on EDN - 1750000175
• Apple-Designed Chip Marks Strategy Shift

It's intriguing that Apple has consciously decided to build an advanced chip design organization, since they are a consumer electronics company. There are comparable alternatives for single-chip mobile device computers, including the Qualcomm Snapdragon and NVIDIA Tegra. What's Apple's angle in doing it themselves? Is it just their obsessive need for secrecy? Or will they somehow integrate differentiating functions that justify the large investment and risk of running a chip design operation? It flies against the industry trend (which PC manufacturer designs its own chips?), but let's see how this plays out. I'm not foolish enough to dismiss Steve Jobs' ability to Think Different.

Anticipating the (40nm) Deluge

Image courtesy Wikimedia.

A short but encouraging news article at X-bit labs, TSMC’s Problems with 40nm Process Technology Largely Over, reports that TSMC has solved its widely-rumored yield problems with its leading-edge 40nm process. Hallelujah! This would be great news for TSMC, their customers, their customers' customers, ...

An interesting side note is the claim that at present only ATI, graphics business unit of Advanced Micro Devices, Altera and NVIDIA Corp. use TSMC 40nm process technology. Really, only three production users of 40nm? Apparently the design pipeline is getting stretched out over many generations, including 65nm on up to 130nm. Ah, I miss the good old days of 130nm design.

(Tip o' the hat to Daniel Nenni for the "tweet" tip.)

College Degrees and Career Salaries

Interesting college/career data to share with your kids (or young people who might actually listen to your advice).

Best Undergrad College Degrees By Salary

Methodology Annual pay for Bachelors graduates without higher degrees. Typical starting graduates have 2 years of experience; mid-career have 15 years. See full methodology for more.

Best Undergrad College Degrees By Salary

The Glass is Half ...

Saw a couple of interesting blog posts/articles recently. Daniel Nenni's data-rich 2010 Semiconductor Forecast made me feel quite bullish about the near-term prospects for our industry. Update: EE Times' Top 25 predictions for semis in 2010 are specific and considerably more dour than Mr. Nenni's forecast.

The other is ominous for the long-term: Is Moore's Law near its end? - Now Hear This! - Blog on EDN. But really, running out of steam in less than five years? Be sure to read the comment stream, as there are some good additions there.

My perspective is that a near-term uptick is certainly overdue. By all indications, the US economy is starting to recover, and with it, consumer spending on electronics will get a nice boost. There's certainly a lot of innovation being shown at the Consumer Electronics Show this week.

As for Moore's Law, I think it keeps working as long as we're using planar CMOS. If we have to transition to fundamentally different materials, or 3D structures, all bets are off.

Mordac is alive and well ...

Apparently Dilbert's "Preventer of Information Services" has taken Core Concepts of Information Systems Security, X52.9380 and is thriving at Synopsys.

Can you tell I had to reset my SolvNet password today? Does Synopsys really hate customers this much? My feelings haven't changed since I last changed my password.

A Secure Job

As attacks increase, U.S. struggles to recruit computer security experts raises an intriguing career possibility for engineers with a solid grounding in computers and networking. I wonder what's required to become a bona fide security specialist?

I'd like to to wish you all very happy holidays, however and wherever you celebrate them. With the recovering economy, may we all have a happy and prosperous 2010.

CS Gravitas

It's hard to imagine greater evidence of a tremendous impact on computer science than authoring the most cited paper in all of computer science as well as in EDA. Remarkable! Before you follow the links, can you guess the subject of the paper?

Find the answer in Gabe Moretti's Kaufman Award Dinner Notes. Good links and amusing pictures are in the coverage at SCD Source. And to delve deeper into the subject, see the Wikipedia article.

Building Blocks of EDA

Some of the unsung enablers of EDA innovation are the companies providing building blocks for common infrastructure tasks. Especially if you're a startup trying to bootstrap an innovative algorithm idea, it's crazy to develop yet another HDL parser or schematic viewer. I was reminded of these products as I read the latest press release from Verific Design Automation, which produces rock-solid HDL front ends for a number of commercial and in-house EDA tools.

The original player in this market was Interra Systems. A great schematic front end is GateVision, available from Concept Engineering. Are there any other major infrastructure providers I've overlooked?

That Light at the End of the Jobs Tunnel

Recently I posted some hopeful anecdotes about the job market for semiconductor design engineers.

Now I read Tech layoffs continue, despite signs of economic improvement and it makes me feel my prior observations are the exceptions to the rule. What's your sense of the current job market? I'm hoping that my new found pessimism represents "capitulation", that point when hope is lost, and marks the nadir of a market or trend.

Engineering Halloween

He only pokes fun at Marketing a little bit this time.

I must confess, I once dressed as an integrated circuit for Halloween. It was in college and I was a DIP. Maybe that's why it didn't impress the girls? Have a great weekend.

Are You Listening?

When I'm out and about doing chores or exercising, chances are I'll be listening to my iPod. But more often than not, I'm listening to podcasts rather than music. Listening to podcasts is an efficient way of "reading on the go". You can catch up on the latest news stories, political opinions, or investment ideas. Those are my interests; you can find a podcast on practically any topic.

Have you listened to podcasts? Which are your favorites? In our field of semiconductor engineering, there's not a wealth of content. But here are some of my favorite engineering/technology podcasts to get you started.

1. IEEE Spectrum Podcast, which is described at Podcast Picks.
2. Science Friday by Ira Flatow. A classic high-quality program from NPR.
3. Security Now by Steve Gibson and Leo Laporte. It's mainly about computer security, but you can also learn the latest on PC software and networking by listening.

It's easiest to subscribe through iTunes, but there are other ways using the RSS feed and a "podcast catcher" program. Happy listening!

Synopsys Users' Group CFP

As you may have heard me say (write) before, the Synopsys Users' Group (SNUG) conference is the most useful conference I attend each year. If you're involved in chip design and haven't attended, you really need to check it out. There are conferences around the world, but the biggest one is in Silicon Valley every March.

Why am I bringing this up now? Because the Synopsys Users Group - San Jose Call for Papers is open! Here's a chance to show your chops and burnish your resume by demonstrating the cool stuff you're doing with Synopsys tools. The authors get a lot of support from the experience Technical Committee [full disclosure: I'm a member] to help develop their presentations and papers. Think about it, and I'll see you at SNUG.

Career Thoughts

Image courtesy Wikimedia.

Taking a break from the technical, career issues merit reflection and discussion. Here are some brief thoughts.

How's the Market?

What's your perception of the ASIC/EDA jobs market? My take is that it's pretty weak, but a number of companies are "selectively hiring". I had a couple of friends leave their struggling design services firm, and they were able to land jobs at established growing companies within a couple of months. On the other hand, there are plenty of engineers who have been looking for many months.

One differentiator is that hiring favors leading-edge experience (e.g., expert P&R and design closure of 65 or 45nm chips), or knowledge (e.g., advanced degree with an emphasis on an emerging hot area).

Natives Say No

With the depressed job market, this isn't the best time to wonder about this, but I'm perplexed at the lack of US-born chip design engineers. Of course, it stems from the lack of US-born engineering graduates. This leaves me scratching my head--engineering jobs are not THAT bad. As a matter of fact, they're one of the fastest ways to earn a very good paycheck out of college, with intellectual challenge to boot.

A downside is that engineering isn't the most secure career around. There are regular risks of downsizing or technological obsolescence. It's not a cushy career, but how many are in this age of globalization?

If you want a secure career, at least medicine and law are "less outsourcable". However, if you really want societal respect, security, and a guaranteed comfortable retirement, I recommend becoming a fireman.

Give US Your Best and Brightest

In the US, we are so fortunate to attract many of the best and brightest scientists and engineers from the rest of the world. There can be complaints about "H-1B abuse", but there needs to be a system that allows the country to benefit from the great contributions possible from immigrants with advanced degrees.

Where Do Seasoned Engineers Go?

While I'm not there yet, friends and I do wonder where all the full-career engineers are. Look around you -- do you see many 50-something engineers? I don't, and I wonder. Do they all transform into real estate agents? Or should I worry about a future as a Walmart greeter?

Others Weigh In

1. As I was preparing this post, a timely and provocative article appeared in EE Times, U.S. engineers at a disadvantage . The discussion in the comments is fascinating.
2. Update: Harry the ASIC Guy and his commenters weigh in on outsourcing, and IBM's aggressive program in particular.
3. Update: Lou Covey has analysis and advice at We're in this boat together. Start acting like it.

Everybody's Getting Physical

Image courtesy Wikimedia.

Back before "nanometer design", there was "deep submicron design", and ASIC synthesis users became very concerned about interconnect effects on timing. The first attempt to deal with this was through "Links to Layout", and especially a whole slew of custom wireload model (CWLM) strategies. If you look at SNUG programs a number of years ago, there were more CWLM papers than you could shake a stick at.

A major advance in accounting for interconnect effects was when synthesis tools started to perform "virtual layout" as part of the optimization-estimation-timing analysis loop. The most notable tool to do this was Synopsys Design Compiler Topographical. My colleagues and I did evaluations of DCT starting with 90nm designs, and data indicated better correlation and generally a better netlist for Place & Route.

As we progress from 90nm to 45nm and below, physical considerations are becoming ever more sophisticated. The latest examples are

• Synopsys Design Compiler Graphical. Includes congestion prediction and some congestion relief algorithms.
• Cadence RTL Compiler's New "Spatial Technology", the latest physically-aware RC feature.
• Oasys RealTime Designer. "RTL physical synthesis."

The Skeptic Weighs In

While "getting physical" has the feeling of more accuracy and general goodness, TNSTAAFL. Though I hope for better quality of results and predictability, I see the following drawbacks

• It forces the logic designer to learn physical design details, and learn new tools or coordinate with a physical designer. While that's nice to know, it takes away from the RTL creator's time to focus on architecture, design and verification.
• The optimization process itself will either take longer (to perform the "virtual layout"), or results will be less-optimal, because optimization time will be taken away in order to run physical algorithms.
• Some of the effort may be wasted, especially for detailed buffering and gate sizing. For example, some P&R tools "throw away" the incoming netlist's buffering and sizing, and re-optimize in the physical domain. So, that effort in logic synthesis is wasted (other than its predictive benefit).
• While WLM-based synthesis is well understood and mature, these physical tools are not. It may take a long refinement period for the tools to produce reliable netlist quality and consistency.
• Some of these tools can't decide if they're logic design tools, physical design tools, or some mish-mash of both. In their efforts to be accessible and affordable for logic designers, they may lack the physical design functions and data access needed to do the job right.

Over the coming months, advanced synthesis users will be putting these latest tools through their paces with real designs. And we'll start to learn whether the added complexity and cost leads to better implemented designs. If not, we can always go back to our old friend the wireload model, trying to get to P&R quickly, where the rubber really (not virtually) meets the road.

Update: I stumbled upon a detailed reply/rebuttal over on the Cadence Logic Design blog! Jeffrey Flieder, thanks for writing this. I very nearly overlooked it.

Found at DAC

My pre-DAC post Looking Forward to DAC laid out what I hoped to investigate by visiting exhibitors, namely

• Low Power
• Datapath
• MCMM
• parallelism
• Asynchronous Design

Well, despite my best-laid plans, I wasn't able to check all these items on my list in two days of roaming the exhibits floor. In some cases (i.e., Asynchronous Design), I didn't find an appropriate vendor. In other cases, my schedule or the vendor's appointment constraints didn't allow me to gather the information. But DAC was a great opportunity to see many vendors, and by careful plan or happy accident, I was able to visit many interesting companies. I'll group my vendor impressions into these categories:

High-Performance Design

• It seemed like Oasys Design Systems was the most talked-about implementation vendor at the show. As I've said before, their capacity and run time claims are incredible. At this show, they put a lot of emphasis on making their claims credible. They've got some customer testimonials to validate them, and their closed-door demo suite explains what's revolutionary about their physical synthesis approach, and why it could be dramatically faster than today's synthesis tools. Update: Harry the ASIC Guy explains technical details of Oasys' approach.

  And to top it all off, I just about ran into Joe Costello on the DAC floor. (He was suspiciously near the Synopsys booth at the time.) It should be great to have Joe back in the EDA industry. I like and respect Aart de Geus a great deal, but Joe Costello can add motivation and excitement back to an industry that's feeling tired.

• Micro Magic is an interesting small design/tools company that's been around almost 15 years. Because DAC wasn't very crowded on Wednesday, I could walk into their booth and have a long informal chat with their CEO. He exudes confidence and credibility.

  One of their tools is a Datapath Compiler, which is one of the few commercial solutions for maximum performance datapath design. Other companies have come and gone (Arcadia is long gone; Arithmatica wasn't at DAC), but Micro Magic apparently has numerous real success stories. (Their customers seldom allow themselves to be named.)

• iNoCs is an early stage startup with tools to synthesize Network on Chip (NoC) IP. Their debut was especially timely because NoC was one of the technologies featured in the Wednesday Keynote by Bill Dally, Stanford professor and NVIDIA Chief Scientist. As it turns out, the connection is even stronger. iNoCs is advised by noted EDA professor Giovanni De Micheli, who has been a colleague of Professor Dally.

Parallelism

• The only company I met with a heavy focus on new parallel computing products was ACCIT, which is developing highly accelerated SPICE simulators running on ATI GPUs. Looking forward to the NVIDIA CUDA port, guys!
• Of course, many of the big EDA vendors are adapting their products for multi-core technology, for example Synopsys PrimeTime Multicore.

ESL Synthesis

I spoke to a few vendors in this space, but I wouldn't dare pretend to have a good grasp on where the field is at. Several journalists and bloggers are writing "now is the time for ESL synthesis", but I have yet to meet the designers using it or even enthusiastic to get into it. It's puzzling to me. There apparently are specific domains with considerable success, such as wireless and image or video processing. And there are specific geographic areas adopting it first, namely Japan. But for the mainstream ASIC designer, I don't yet see it catching on.

Others

I liked what I heard in a brief visit with Imera, which develops hardware+software solutions to allow secure remote debug of software (e.g. EDA tools). In my work, there is constant antagonism between the EDA vendor, whose engineers claims they cannot debug their software beyond their walls versus the EDA customer, which doesn't want the "company jewels" of full-chip RTL or netlists to ftp over to the EDA vendor. Imera has solved the problem with a distributed debugger and networking solution that allows the R&D engineer to debug from the vendor side, while the EDA tool is running on the design data at the customer's site. Sounds like it would resolve the stalemate and allow us to get on with the problem-solving.

Overall Impressions

I had not attended DAC since 2006. It was a little disorienting because of all the changes in the industry and the conference itself. Attendance was way down from boom times. For the first time, I had an "exhibits only" pass, which allowed me to go up every day and visit the exhibits floor but not the technical program. After Free Monday, the floor was much less crowded, and it was a pleasure to walk right up to any vendor and get all my questions answered. One irritating practice of several vendors was to not have any open demos, but to require a one-hour appointment to be scheduled for a closed-door meeting. I found this quite inconvenient for any sort of spontaneous discovery, and as a result both vendors and I missed out on some worthwhile discussions.

I was glad I attended DAC. I obtained information that will help me in my job, and met old and new friends. I wish for the sake of the organizers and the exhibitors that attendance had been stronger, but the economy was a strong tide to fight. Let's hope that tide is turning and the 47th DAC in Anaheim will celebrate a growing vital EDA industry.