"Hi, I'm a RealTime Designer. And I'm a DC."

Look what one can miss by not attending DAC! I didn't realize that Oasys put together a bunch of videos poking fun at Synopsys (and ripping off Apple's commercials). See Oasys' DAC videos. I would have liked some more inside jokes about the competition's shortcomings, but we get the general idea.

As a bonus, the well-produced DAC 2009 video features company executives in a music video with cheesy parodies of some classic rock songs. I'm amused, but Al Yankovic need not worry.

Props to DeepChip.com for leading to my discovery of these gems.

What's inside Verizon’s Apple iPhone?

Verizon's version of the iPhone is just out and a couple of "teardown" companies have already sacrificed samples to see what's inside. Steve Leibson has their parts lists at Teardown of Verizon’s Apple iPhone reveals chips used. Want to know how many and which ones? Want to see the video teardown? | EDA360 Insider.

Most Dominant Franchise in EDA

I got to wondering -- which tool has the biggest lock on a major piece of the EDA tool constellation? (I originally wrote "monopoly" instead of "franchise", but don't want to connote market manipulation.) From my perspective, three come quickly to mind

• Cadence Virtuoso
• Synopsys Design Compiler
• Synopsys PrimeTime

You may have other ideas, and I'd love to hear other nominations. Of these three, I think a good case can be made for Design Compiler having the strongest position. The other tools have large market shares, but also competition determined to make inroads.

Who might chip away at the synthesis gorilla? The old and new rivals are Cadence RTL Compiler and Oasys Real Time Designer. Just published on ESNUG is this "marketmonial" (I need a word for a marketing-inspired testimonial): DeepChip.com: "An Oasys RealTime Designer vs. SNPS DC-Topo/DC-Graphical benchmark . A couple of things that I especially like about Oasys' approach:

• If Oasys truly optimizes at a higher level of abstraction (physical feedback can change the way RTL structure is synthesized), then substantial performance advantage claims become believable
• It freely exports DEF and integrates with the physical design world. By contrast, DC Topographical/Graphical can't decide whether it wants to be complete physical synthesis or "PD-lite", not fully supporting or integrating with detailed physical design data. (RTL Compiler is open like the Oasys tool in this regard -- it interfaces with Encounter P&R tools using standard data exchange formats.)

Time will render the verdict, and the EDA battlefield is littered with past attacks on DC's franchise, but we need competition in all tool areas to continue advancing the state of the art.

Oops!... Intel Did It Again

Intel, if you need reliable designs to support your latest CPUs, there used to be a variety of companies in the chipset business.

January 2011 had more than its fair share of bad news for Intel, culminating in a very expensive recall of their newest chipsets because of a design defect. Most of the press coverage focused on the financial hit, but us design engineers are dying to know "what happened?". What's most interesting is that the problem isn't a defect that manifests itself right away, but one the causes the component to deteriorate over time. At first, I thought "electromigration". But the best speculation/analysis I've seen this early has been from Mike Demler, who shares his theories in Price for a new SATA I/O $700M. A complete AMS verification? Priceless! and If ever EDA needed a ($700M) proof point on their value....

If that's the root cause of this problem, it's another data point showing fraying at the edges of our tried and true EDA suites: tools are not available or mature to help with analyzing reliability, materials, packaging, etc.

Update: Thanks to a link from Steve Leibson, I came across this very specific description and analysis of the problem.