Wondering about the IEEE

I feel like I should be a member of the IEEE. I am, this year. Throughout my career, it's been an on-again, off-again relationship. Even when my company reimburses me, sometimes I feel that it's not worth it.

What I want it to be

• Teach me about new developments in my specialty. There are some gems, but it's harder to find from IEEE publications vs. trade publications like EE Times or EDN. Part of it is because I can't find a Society/Publication that aligns well with my specialty (see Gripes, below).
• Teach me about interesting developments in other specialties. The articles need to start from a basic level, not trying to prove how sophisticated and complex the author can be. I am not finding this from the IEEE. Something like Scientific American or Discovery magazines might be a more accessible resource.
• Represent my professional interests. The IEEE-USA tries to do this, and I'm a member. But membership is optional, and I wonder how many USA EEs belong or are even familiar with it?

What IEEE should do

• Give a primer to members on how the IEEE works. I have sort of figured these things, but why doesn't the IEEE come with a "user's manual" to address these dead-on?
  • What is a Region and what's a Chapter?
  • What is the difference between their publications Spectrum, Proceedings, and Transactions?

Other gripes

• There's no Society for Digital IC (RTL & Gates) engineers! I just can't figure this one out. There are certainly Societies for semiconductor process, circuit design, and packaging. But what Society should a plain-ol' ASIC engineer belong to? Why isn't there a perfect fit for such a common EE discipline?
• The price/performance of an IEEE membership really seems out of whack. Why does it cost me (or my company) over $140/year, when the main benefit is a magazine subscription or two? Why, I can subscribe to EE Times for free and get far more practical news and technical information! Where is all the IEEE money going? To some huge bureaucracy in New Jersey?

What do you think about the IEEE? Do you belong? Why or why not?

EDA standards development within the IEEE is mismanaged

Come on, Gabe, tell us what you really think about the IEEE DASC: EDA DesignLine | EDA standards development within the IEEE is mismanaged

It's quite an indictment about what ought to be one of the most prestigious standards bodies related to EDA.

I know that most EDA vendors have groups whose full-time responsibility is the care and feeding of standards groups. In an ideal world, they'd be ensuring the most elegant and implementable open standards. The Internet standards bodies seem to be a fine example of this, and have delivered interoperable standards that spurred an incredible information revolution over the past decade. Why can't the EDA industry have that, too?

In reality, the EDA vendors do quite a bit of political maneuvering and intrigue. For example, we might only have to deal with one HDL if Cadence had opened up Verilog before VHDL emerged. Imagine the tremendous resources spent on VHDL that could have been saved. We almost had two library standards because Synopsys wouldn't open up the "Liberty" format until there was a revolution brewing to move the industry to DCL/ALF formats. You've never heard of DCL and ALF? Well, Synopsys finally opened up .lib and no one needed those alternate formats.

Anyways, getting back to Gabe's post, it's sad how quickly the proposed low-power standards are degenerating into political battles between EDA companies, much like the CCS vs. ECSM library standoff. Cadence's initial proposal sounded pretty reasonable, though perhaps I'm naive to think that they and Synopsys could have agreed on a common standard.

A Good Chip News Site

Geek.com's ChipGeek page is a good source of semiconductor news items. The analysis and commentary by the editor adds helpful "color" to the pure news. If you dive down into the readers' comments, they range from wonderfully instructive to embarassingly sophomoric.

By the way, the EDA blogs I follow seem awful quiet! Are people burned out after DAC? Or is summer over and it's time to get back to work?

But, on the professional blogging front, a shout out to Gabe Moretti, who is editor at EDA DesignLine, a new web site of the CMP tech publishing empire.

YAST - Yet Another STA Tool

I'm initially puzzled when an EDA vendor fields a new tool to take on Synopsys PrimeTime, e.g., Incentia Timing Analysis and Constraint Management Software Adopted by Ambarella.

PrimeTime is one of Synopsys highest-quality, most trouble-free tools. The main gripe I have with PT is that it can only tell you about timing problems -- it doesn't fix them! Hence, a cottage industry of home-grown scripts and supplementary tools exists to take PT reports and generate ECOs to fix the violations.

However, some of the features in this TimeCraft tool sound pretty attractive, and give me second thoughts about assuming nothing can beat PrimeTime. Attractive features include

• MSV support
• "multi-task capability for multi-corner and multi-mode analysis"
• Advanced OCV features
• Constraint Manager

Charter for a Corporate CAD Group

I discovered another EDA-related blog, Cool Verification. Cool Verification: Creating Corporate Standards? Beware... is an excellent post outlining the considerations in creating and managing a "Corporate CAD" department.

I've taken this group's mission for granted, but my company didn't even have such a department four years ago, even as it was cranking out huge industry-leading chips. What finally pushed us to create a central group was the proliferation of derivative chips and especially the diverse chips being designed by new business units. It no longer made sense to have a few "designers with a tool fetish" responsible for creating and maintaining all the flows. Hence, a CAD department was born. The referenced post touches upon the dynamics of trying to please all groups in the face of different requirements and priorities.

EDA Confessions, Part I

After my prescient DAC trip report, I've been thinking of a couple of times in my career when I've really missed the boat on EDA companies. I have a couple of examples that I can't forget. I'll write about them one at a time. Confession is good for the soul. ;-) The first is a company that I ignored, yet in retrospect could have done a great jobs for us.

The Time

Late 1990s

Product Type

Floorplanner

The Company

Silicon Perspective (SPC)

The Problem

My company was working with Synopsys on "Chip Architect" and "Floorplan Manager" to close timing on "deep submicron" designs. These were around 0.35 micron, IIRC. I never used Chip Architect, but my colleagues were beta testing and helping to debug it. I spent a lot of time with Floorplan Manager; it was pretty inefficient to back-annotate tons of layout data onto Design Compiler, and for DC to optimize designs in a way both effective and feasible for physical design. We were struggling to close timing on the design.

The pitch

An SPC Sales guy kept calling me, asking us to evaluate FE. He made extraordinary claims about its performance, capacity, and quality of results. He wanted us to try it on a multimedia design one of our groups was working on.

What I did

I couldn't believe that this little startup could deliver such amazing results that Synopsys and Cadence couldn't! Clearly, he was just making wild claims to get our attention. So, I never did bring him in for an evaluation.

What happened

Our design project took so long and it was eventually cancelled. And I ended up leaving the company around the same time. Later, SPC was acquired by Cadence for a large sum and today is the foundation and namesake of "Encounter", their whole family of Digital IC implementation products!

Lesson learned

Don't dismiss startups lightly! Consider them skeptically, but give them a chance if their story seems plausible.

Graphics Beginners' Guide | Tom's Hardware

Graphics Beginners' Guide | Tom's Hardware is a great introduction for understanding (and purchasing :-) today's graphics cards.

It's a series of three articles, all of which are accessible from this page.

After the AMD / ATI merger: Will Nvidia GeForce still compete with ATI Radeon?

After the AMD / ATI merger: Will Nvidia GeForce still compete with ATI Radeon? | TG Daily is the best in-depth analysis I've seen of the implications of the AMD acquiring ATI. It lays out a number of scenarios, but the end game is far from clear.

2006 DAC Report

Introduction

The "hot" areas of EDA these days are Electronic System Level (ESL) and Design For Manufacturing (DFM). Indeed, there were numerous companies offering things such as SystemC design or yield-aware layout tools.

I attended DAC for one day, Wednesday. I focused on low-power and variation-aware tools, and compiled a list of companies participating in these areas. I had time to see about half the companies I identified. Below is a short summary of my impression of those companies.

Companies that Impressed

• Azuro. Low-power clock design. They optimize clock gating and physical clock tree for low power. They claim 15-25% less power than using today's tools. This is a niche tool that is worth looking at. The most impressive thing I saw at DAC was their clock tree analysis/visualization tool. At a glance, the design can visualize the structure and quality of the clock tree. It's better than any analysis I've seen before.

• Altos. Library characterization, including statistical effects. Their characterization system, Liberate, includes their own very fast SPICE-like engine. They claim ~10X faster than today's tools. They can generate .lib and also the latest CCS and ECSM models. They appear to have a solid grasp of what's needed for statistical characterization, and their high performance will be very welcome for that. They're working to support SSTA from Extreme DA. The founders are from CadMOS (SI tool acquired by Cadence) and seem sharp. They recently published an article in EE Times. [Note: Magma just announced an upgrade to their characterization system.]

• Proficient. Low-power design. Intriguing. It seems like a pretty small company.

• Prolific. Post-layout power & timing improvement. Their tool may be useful and the approach is sensible and simple (bolting onto PrimeTime). Designers could do something like this themselves, but if their tool is reasonably priced and effective, it may be worth it.

• TSMC. They conducted a series of advanced methodology presentations. It is impressive how much they've thought through the whole methodology and worked with EDA vendors on their "Reference Flow 7.0".

Companies that Didn't Impress

Censored! I'm don't yet have John Cooley's nerve to dis companies in public. In my case, it wouldn't really be fair to opine on them after a half-hour presentation or demo, anyway.

Other Notes

• "Power Forward Initiative" lunch hosted by Cadence. This is a consortium initiated by Cadence to develop a standard "CPF" Common Power Format description of low-power design intent. CPF would drive implementation, checking and analysis tools. Something like SDC is for timing. This may bear fruit in a couple of years, but of concern is that Synopsys is not on board. Will it be another political fight like CCS vs. ECSM? [Yes, the politics have already started with a Synopsys counter-proposal.]
• Coincident with DAC, Synopsys announced enhancements to PrimeTime and Star-RCXT with statistical capabilities.

Best Freebie

There didn't appear to be major schwag as I remember from years ago. I remember when you could always count on Viewlogic for a bat or a hockey stick, or Altera for a soccer ball. However, one gift at this year's DAC impressed me. It was the hand-held fan from Bluespec. It appears to be your standard simple battery-powered fan. However, there are LEDs embedded in the fan blades, and when you turn it on and the fan spins, the lights spell out promotional messages for Bluespec. Pretty "cool"!

Other Coverage

• EE Times DAC Coverage
• EDN DAC Daily Report
• Gary Smith's What to see at DAC List
• John Cooley's Cheesy Must See List for DAC 2006

Cooley's Must See List for DAC 2006

It's unfortunate I didn't see this before going to DAC, but EDA Gadfly John Cooley posted an extensive Must See List for DAC 2006.

John's list is quite long, spread out over 24 categories. Rather than being very discriminating, it's more of a concise summary of all that's new and significant at DAC.

Companies Common to Cooley and Busco Lists

• Altos - Statistical timing characterization
• Apache - IR drop analysis.
• Athena - simultaneous timing closure (post-route)
• Azuro - low power clock implementation
• ChipVision - Low-power ESL design
• Extreme DA - Statistical STA
• Forte - SystemC synthesis
• Magma - Talus implementation system, Blast Fusion design closure
• Prolific - post P&R timing optimization
• Sierra DA - physical synthesis & routing.
• Zenasis - custom cell generation for timing optimization

Companies Common to Cooley, Smith, and Busco Lists

• Apache
• Forte Design Systems
• Magma DA
• Sierra DA

Gary Smith's Must-See List

Coincidentally, just after posting my DAC must-see list, I see the list of veteran EDA industry observer Gary Smith. His list is broader than mine with a good dose of "ESL" and "SVP" vendors: EETimes.com - Imperas tops analyst Smith's watch list

Looking for intersections, we both mentioned the following vendors:

• Apache
• Forte Design Systems
• Magma DA
• Sierra DA
• Proficient Design

It appears that I don't share Gary's enthusiasm for ESL, and he really doesn't share my enthusiasm for "statistical" or "variation" analysis.

DAC is Here!

EE Times is doing a nice job of covering the Design Automation Conference, which started yesterday in San Francisco. Road to DAC: Complete Conference Coverage has lots of articles and even a set of webcasts that includes an interview with Joe Costello, former Cadence CEO and EDA celebrity.

Thought I'd post the list of companies that I'm interested to visit. It is far from a comprehensive list, but these are companies mostly in the "design implementation" space that piqued my interest based on what I've read.

• Altos - Statistical timing characterization
• Apache - IR drop analysis.
• Athena - simultaneous timing closure (post-route)
• Azuro - low power clock implementation
• ChipVision - Low-power ESL design
• Extreme DA - Statistical STA
• Forte - SystemC synthesis
• Magma - Talus implementation system, Blast Fusion design closure
• Proficient - Low power design
• Prolific - post P&R timing optimization
• Sierra DA - physical synthesis & routing.
• TSMC - Reference Flow 7.0
• Zenasis - custom cell generation for timing optimization

EDA Players Detail Involvement in TSMC Reference Flow

EDA Players Detail Involvement in TSMC Reference Flow - 7/18/2006 - Electronic News details which EDA vendors are providing which tools and technologies for TSMC's recently updated "reference flow".

With respect to statistical STA, an area of interest to me, the article sites support from Cadence and Magma, but not Synopsys. That's funny, I don't think of Cadence as a player in the timing space. They don't even really have an STA tool, do they? I thought all their customers sign off on PrimeTime.

TSMC Flow Adds Statistical STA

TSMC (Waferzilla?) has announced the latest additions to their Reference Flow, version 7.0. The two main additions are Statistical STA and more Power Management features.

Interesting that the Statistical STA flow supports vendors Magma and Synopsys. Magma has been promoting their Quartz STA tool. Has Synopsys announced a Statistical STA tool? I don't recall seeing it.

And, what about library support? How will this be done? I haven't seen any standards offered for representing variation in Liberty format, for example.

Overall, this announcement is a hopeful sign, but I wonder how real it is, or when we might actually see a working flow.

Statistical Characterization and STA Primer

Cell model creation for statistical timing analysis is a great primer on Statistical Static Timing Analysis (SSTA). It's written from the viewpoint of the challenges facing statistical library characterization. After reading this article, I wonder how we're *ever* going to have a complete set of SSTA-characterized libraries. Fortunately, the EDA startup Altos, which is where one of the authors works, has a solution under development. Unaddressed by this article is how such characterization will be represented for all the vendors' STA tools. As of now, there is no .lib "Liberty" standard for statistical modeling. We've got a long ways to go!

Metcalfe's Law is Wrong

IEEE Spectrum: Metcalfe's Law is Wrong gives in-depth analysis to one of those laws that people accepted uncritically.

I don't know what analysis Metcalfe's original "law" was based upon, but it doesn't seem as robust as Moore's law. The paper referenced here goes on to hypothesize what the law regarding the value of networks should have been. It dovetails nicely with another concept, the "long tail", that comes up when discussing e-commerce, blogs, and many other phenomena.

DAC's 44 New Exhibitors

Do you know much about these new EDA companies? 43rd Design Automation Conference to Feature 44 New Exhibitors They're news to me. Which ones will capture enough interest to thrive?

Power Primer

Power Management DesignLine | Low Power CMOS Circuit Design is an excellent survey of CMOS power consumption along with the most common techniques to reduce power.

This article is a good quick reference -- why, these questions might even come up in an interview! ;-)

Hot Summer for CPU Companies

Hot Summer for CPU Companies is a nice summary of the recent CPU wars, and how Intel Israel's designs may yet save the bacon of "Chipzilla".

I wonder what tricks they're using for power-efficient design?

Lies, Damn Lies, and Engineering Manpower

Heard the One About the 600,000 Chinese Engineers? is very interesting for how a set of poorly-vetted data can take on a life of their own.

I've heard the IEEE-USA referring to such numbers, too. I think their interest is a combination of wanting to strengthen American competitiveness, but also to ensure increased funding for engineering education and research. In other words, self-serving for the greater good!

Cadence Powers Forward

I wasn't sure to make of Cadence's announced Power Forward Initiative. This is such a nascent field, do we know what to standardize?

But then I could think of some design practices that would be very good to have a standard way to describe and verify, such as what voltage and power domains various parts of the design should be connected to, what is the design convention for isolation and level shifting, etc.

This could be a useful standard. Let's hope it doesn't degrade into another Cadence vs. Synopsys "we have two standards so we have no standard" like ECSM and CCS libraries!

Semi Business is too good? Allocation, here we come!

The headline EETimes.com - TSMC puts customers on allocation certainly caught my eye and made me think of the good ol' days.

But reading the fine print, this is only for older geometries, i.e., 0.18 and 0.25 micron. Even though there ought to be lots of "second-tier" fabs with capacity, especially in China, the article explains that it's difficult to port mixed-signal design from one process to another. Once you go to production with a particular foundry on these types of "touchy" designs, you are in bed with that foundry for a long time!

TSMC DFM format empowers fabless design

Good news! Fabless semiconductor vendors (e.g., NVDA, BRCM, etc.) won't be up a creek in getting yields at 65nm and below: EETimes.com - TSMC DFM format empowers fabless design

If this works as advertised, this collaboration will enable TSMC + EDA vendors to work like an Integrated Device Manufacturer (IDM), and not suffer from walls and insufficient information sharing.

I'm looking forward to the TSMC Technology Symposium, which is always good for seeing how the foundry world operates, and what interesting issues they address that we seldom hear about in the "front-end" design world.

Startups to watch

This is an intriguing list of startups, though the selection criteria is rather mysterious. Reviewing it gives you a feel for what's coming and what's hot in our industry. I spotted a few EDA companies, several in the "DFM" space and at least one related to "ESL" design.

"editors have selected companies based on a mix of criteria including: technology, intended market, maturity, financial position and investment profile.

Startups on the Silicon 60 list include companies involved in semiconductor chips, memory, fab equipment, packaging, foundry, materials, MEMS and EDA software that made an impression on EE Times editors. They are emerging companies to watch for a wide variety of reasons.

EETimes.com - EE Times updates list of emerging startups

PS3 Prediction: Sailing Past Xbox 360 on a Sea of Red Ink

GameDaily BIZ: Sony's Game Division Expecting Massive Loss on PS3 Launch

UNDERclocking, anyone?

Those darn ATI chips are "hot", alright: Apple purposely slows MacBook graphics chip.

GPUs are just so huge. It's an "embarassingly parallel" application, so ATI & NVIDIA can just keep throwing more gates that the problem, following Moore's Law. The Holy Grail is to render cinematic quality in real time. We'll get there some day, but there will need to be lots of technology and methodology innovations to use power wisely.

Building up a `bump' in the new flat world

I attended an alumni event, Berkeley in Silicon Valley, earlier this week. It was at the Computer History Museum in Mountain View, which is definitely worth a visit for the audience of this blog. Ah, the memories! They have all the early PCs, and really old mechanical or analog computers, slide rules, etc.

The featured speaker was Professor Richard Newton, Dean of the UC Berkeley College of Engineering (my alma mater). I was going to post a write-up of his talk, but Mike Langberg from the San Jose Mercury News already did a very professional job at MercuryNews.com | 04/13/2006 | Langberg: Building up a `bump' in the new flat world. So go read that!

Some comments/notes:

• Synthetic Biology is "the next big thing". Remember "Plastics" from the movie The Graduate? Well, this is like that for the next century.
• The questions from the audience were surprisingly pragmatic:
  1. How can we invest in Synthetic Biology? Prof. Newton didn't have specific opportunities. It's an extremely new and risky field, more "research" than "development" at this point. I wonder if Biotech mutual funds would cover this space? It seems like they would.
  2. What about the problem of H1B visas and how that will devalue US engineering careers? I don't think a university professor can really appreciate the anxiety that some engineers in industry feel. Professors see the newest, sexiest technologies and get to work with really interesting emerging companies. Personally, I've become less concerned with H1B than with "offshoring". At least the visa-holders bring their high skill levels and tax-paying ability into the US!
  3. With demographic changes in California, the questioner suggested that the future majority ethnic groups (i.e., Latinos)do not value education as highly, and does this pose a challenge to Prof. Newton's call to make the Bay Area a "bump in the flat world"? Wow, this seemed like a politically incorrect question, and the questioner must have had guts (or been oblivious) to ask it. Prof. Newton didn't cut him any slack, saying that he found the Latinos that he encounters in his work to be just as passionate about education as anyone else.

The State of 3D: Economics of 3D

The State of 3D: Economics of 3D is an excellent history of the graphics chip industry, i.e., NVIDIA vs. ATI, past, present, and future!

Furthermore, as you dig into the article, you can learn a lot about semiconductor economics, die size, binning, and the huge impact that design and fabrication issues can have on economics and business success.

An Awesome DATE Report

Peggy Aycinena has written a very detailed and well organized report on DATE, which is the European equivalent of DAC. Read it all here: EDACafe Weekly : DATE 2006: Between Gem�tlichkeit und Angst - March 13, 2006

Furthermore, she refers to the very impressive keynote address by Mentor Graphics' CEO:

** The keynote address delivered on Tuesday morning at DATE by Dr. Wally Rhines, Chairman and CEO at Mentor Graphics and Chair of the EDA Consortium (EDAC) was nothing short of a magnus opus. Rhines simply said it all - simply.

As an aside, I've never met Peggy, though I recognize her name as a long-time EDA analyst and commentator. This column was the first time I've seen her picture, and I can't help but be struck by her resemblence to Arianna Huffington! (And I mean this in a complimentary way.) Separated at birth? What do you think?

IT Jobs Migration: Fears vs. Reality :: AO

IT Jobs Migration: Fears vs. Reality :: AO is a thoughtful, even-handed review of the job dynamics of the Information Technology field. It refers to an in-depth report by the Association for Computing Machinery (ACM), "Globalization and Offshoring of Software".

I'd assume that the analysis of the IT field applies to the closely related engineering fields like hardware and software engineering. Let's hope that the conclusion is correct, that an open market benefits both developed and developing nations. I'm sure this is true on the macro level, but we must keep an eye on those directly affected by outsourcing -- do companies invest in "new business opportunities to generate more new job"?

RapidChip R.I.P.

Being modest, I hate to say "I told you so", but LSI scraps ASIC line, plans to sell DSP unit seems consistent with the doubts about RapidChip that I expressed in this post in July 2005. Is there a stampede for the doors? A pioneer in the field of "structured ASIC", Lightspeed Semiconductor, exited the market just last month.

Too bad, I was sort of longing for the simple days of yesteryear when we did Gate Arrays, and these products resembled re-warmed Gate (or Embedded) Arrays.

SystemVerilog, a better RTL

I'm looking forward to being able to use SystemVerilog for Design (synthesis). Looks like this effort is picking up according to EETimes.com - Vendors warm to SystemVerilog

I haven't done a thorough survey of the language, but a few of the things that will help Design/Synthesis are:

• Interfaces (objects that define ports (and even protocols) between designs)
• Explicit treatment of intent for case statements
• Explicit treatment of intent for always blocks

I'm sure there are many more. I look forward to trying it.

Is Synopsys undermining synthesis standardization? Gee, they'd never do that. ;-) Looked at from the perspective of protecting their franchise, they have the most to lose from making designs portable. We've the same types of battles over library standardization (finally, Liberty) and a synthesis subset for Verilog HDL.

The 9-in-1 Wonder Chip

I don't get all the hype about the IBM/Sony/Toshiba "Cell" chip: The 9-in-1 Wonder Chip - September 5, 2005

Sure, I can believe it's a very fast, efficient CPU, with provisions for multi-processing. But IBM is betting its whole computing future on it? And how could this be so revolutionarily different from anything that all the other genius CPU designers have come up with, including AMD and deep-pocketed Intel?

I don't get it, but I'd like to. What's so different?

Engineers' pay will fall

Talk about "tough love"! This letter to EE Times, Engineers' pay will fall, presents a reasoned analysis of the dynamics affecting an Engineer's career, particularly in the US.

He has a very concise analysis of the reasons that Law and Medicine seem to provide more lucrative, secure careers now that "The World is Flat".

He doesn't dump on engineering and say to never pursue it as a career, but you need to go into it with your eyes open and priorities straight.

Computer research due for course correction

Research due for course correction lists several research directions for computer design, including

• What's the right granularity for parallelism?
• 1,000 CPU multiprocessor reference system for academic research (RAMP)
• "CMOS killer" and CMOS rejuvenator technologies
• wireless convergence and management
• new software engineering approaches for higher productivity and quality

Fascinating, stimulating stuff. It will keep us engineers busy for a long time. :-)

Analysis & Solution of the American Engineering Crisis

OK, the post's title is grandiose, but it caught your attention. Humorous, satirical, but with a big grain of truth:

"Americans, it seems, have also grown too lazy to bother obtaining an electrical engineering or computer science degree.

How this surprises anyone is beyond me. You can float through four years of undergraduate classes sucking beer out of co-eds' navels, pick up your philosophy degree and then head to law school. Or, if you're one of those pathetic young Democrats, you can pretend to work hard at your politics classes, shoot a few rounds of golf for the school team and then whore yourself for millions in Washington. Less ambitious types can work hard enough in a grade inflation rich system to interest a Fortune 2000 company, flag down an MBA and then spend thirty or so years collecting a nice paycheck.

You'd have to be a real expletive to try and succeed in the difficult engineering and science classes"

America can lick the Asian peril by training Mexican smarties

Trends in semiconductor technology | Gabe on EDA

Trends in semiconductor technology | Gabe on EDA

Great summary by Gabe of an IBM talk on the big technical challenges to scaling CMOS further. Some of the points that caught my eye:

• silicon CMOS is viable for at least 10 years down to around 22 nm range
• Power & leakage management are essential
• next generations of CMOS will change to metal gate and high k dielectric materials. Hey, doesn't the "M" in CMOS stand for Metal, anyway? Why did we start using polysilicon gates and still call it CMOS? Should be CPOS!
• Yield variability is addressed in three categories: lot-lot, regional systematic, and local systematic. ... The real challenge is the local random variations. Because of the atomic scale of the devices, all effects are a function of small number statistics.

NVIDIA should acquire ...

And now, for a business interlude in this blog, What would Jen-Hsun Do?

Jen-Hsun Huang is the CEO of NVIDIA. In NVIDIA's last earnings conference call, management announced the intention to make more acquisitions. The article that I've linked to is a survey of the markets that NVIDIA competes in, and offers a theory as to which company NVIDIA should acquire. Interesting reading! Is he right? Check back in 2007.

One In Two PCs Won't Run Vista's 3D Interface

One In Two PCs Won't Run Vista's 3D Interface, i.e., those with integrated graphic controllers lack the 3D power for Microsoft's new OS user interface.

Sounds like a good omen for discrete GPU vendors like NVIDIA and ATI!

Geeksta rappers rhyme tech talk

EETimes.com - Geeksta rappers rhyme tech talk

This is funny! I must be in the 1 percent of 1 percent of the tech community that appreciates this stuff. Jump to page 3 if you want to get to the lyrics.

Panelists: ESL is promising but still needs work - 2/9/2006 - EDN

Panelists: ESL is promising but still needs work - 2/9/2006 - EDN is a nice survey of what some companies are doing for design above RTL abstraction.

The article acknowledges that the systemC flow has holes. It was interesting to read that people are translating RTL to SystemC. What do you call synthesis in reverse? Abstraction? It sort of makes sense if you get a huge simulation speedup, but robust synthesis and verification from SystemC to RTL would help productivity much more. That is still out in the future for the general case.

Digital designer's plight debated at ISSCC

EETimes.com - Digital designer's plight debated at ISSCC is just full of ideas on the future of careers in circuit and logic design.

I was surprised that there doesn't seem to be that large a market for digital circuit design, as "clever" techniques like domino logic prove to be too power-hungry.

There will be opportunities in mixed signal circuit design or for "those engaged in synthesis and place and route". That's fine by me, as the latter is my area of expertise.

U.S. designers still the best (for now), CEOs say

EETimes.com - U.S. designers still the best (for now), CEOs say is a thought-provoking survey of CEOs perspective.

Note the difference between quality and quantity, number of engineers vs. number of good engineers.

Also interesting is the comment that overseas engineers' salaries are catching up to the US. Good for them! (and for us!)

Development work is five times cheaper here

‘Development work is five times cheaper here’ is the claim by the CEO of ATI Technologies, commenting on their Hyderabad R&D center.

There are certainly very attractive aspects to setting up shop in India, but this article is a little over the top. I wonder if it's because this story is published for an Indian audience, or if it's because ATI has only been doing R&D there for a year, and perhaps hasn't seen the tradeoffs through a full product cycle?

The Power of the Xbox 360 GPU

The Power of the Xbox 360 GPU is a very informative interview with a VP of Engineering at ATI. He speaks in reasonable detail about what's in the custom graphics chip of the Xbox 360 game console. He contrasts it with conventional GPU architecture, and of course espouses why it must be better than what NVIDIA will provide in the Sony PlayStation 3 GPU.

The Xbox 360 GPU, "Xenos", is actually a two-chip implementation, and one of the chips has a big embedded DRAM! Although lots of ASIC vendors talk about doing this, you don't see it often in practice. Performance-wise, it makes sense, as you get huge memory bandwidth via the very wide interface to the DRAM.

SNUG: Synopsys Users Group - San Jose Conference at a Glance

SNUG is coming! The flagship San Jose Synopsys Users' Group meeting starts on March 20, 2006. Here is the conference schedule.

I've always felt this is the best conference for the "in the trenches" chip design engineer. It's very practical, with good tutorials, keynotes, and a healthy dose of user papers.

As I was signing up this year, I noticed that almost all the sessions I signed up for were Panels or Tutorials, not User Sessions. I wonder if the conference schedule is shifted away from user papers this year, or if my interests just happen to be with the other topics. It would be interesting to look at the split of types of sessions over the years. Well, not so interesting that I'm actually going to do the study, though. ;-)

Library standardization effort takes flight

Library standardization effort takes flight

There is a need for standardization of modeling for Statistical STA, though that whole technology is not well understood. It may be too early to standardize!

It would be great to settle the CCS vs. ECSM divide, however. These are essentially the same modeling approach, yet defined differently by Synopsys vs. Cadence/Magma, respectively.

I have sympathies for Si2 in trying to forge these standards across EDA companies. I was more involved in the days of Liberty, DCL/DCM, and ALF standardization, and it was very hard to get cooperation across all EDA vendors. They see Standards as an area to maneuver for competitive advantage.

Leakage takes priority at 65 nm

Leakage takes priority at 65 nm in EE Times is a nice survey of the experience of 65nm IC designs so far.

I noted that Statistical Timing Analysis was called a "must-have" technology, because of all the combinations of operating conditions when you have multiple voltage islands.

Two Win Prestigious Engineering Award - New York Times

Two Win Prestigious Engineering Award - New York Times

Cool! It's nice to see a couple of great engineers prominently recognized for their great contribution to technology (37 years after the invention of the CCD)!

Down with FinFETs, Up with Materials!

EETimes.com - FinFETs may never come in, IBM fellow claims

FinFETs (transistors where the channel gets pinched off from both sides) sound like pretty slick design solutions, and several companies and many universities are studying them. But this IBM researcher predicts that they aren't manufacturable. Instead, industry needs to focus on advanced materials for the traditional "planar" transistor technology.

Managing variations in IC physical design

EETimes.com - Managing variations in IC physical design is a great paper on the design closure challenges facing nanometer-scale IC design.

The author, Shankar Krishnamoorthy of Sierra Design Automation, describes the very typical timing analysis and design closure flow, where many different modes and PVT corners must be considered, yet closure tools only understand one or two of the scenarios.

The rigorous treatment of design variation, classified in a matrix of variablility "causes" vs. "effects", is the best treatment I've seen in a public article. (EDA vendors will show similar analyses when privately pitching their new variation-aware products.)

Surprisingly, the author does not conclude that "statistical" timing analysis, which is all the rage in the EDA community, is a panacea. He points out the difficulties of getting statistical characterization data for process, libraries, and interconnect. He also asserts that Hold time violations require analysis at whichever corner most aggravates a particular violation (calling for multi-corner analysis).

Very thought provoking! It will be interesting to see what products Sierra comes up with to address this growing IC design closure problem.

Teardowns find 'Microsoft Inside' Xbox 360

Here's another, more detailed, Xbox 360 "reverse engineering" article: EETimes.com - Teardowns find 'Microsoft Inside' Xbox 360.

Most of the chips have Microsoft's label on the package. At least in the case of the GPU, I believe that Microsoft bought the design from ATI and is paying royalties. I've read that this is a different business model from that of the original Xbox. Microsoft apparently wants more control over the silicon and any cost reduction efforts.

Microsoft's Red-Ink Game (Xbox 360)

Microsoft's Red-Ink Game provides cost estimates of the just-released and super-hyped Xbox 360 game console. Estimates are that it costs $126 more that the sale price to build the box.

Looking just at the chips, this machine has some expensive silicon:

Semiconductors alone account for $340, -- more than 72% of the materials cost -- iSuppli estimates. One key component, the IBM-designed microprocessor chip at the center of the console (see BW Online, 10/25/05, "Inside IBM's Xbox Chip") costs about $106. Both IBM and Chartered Semiconductor (CHRT) of Singapore are building the chip for Microsoft.

ROOM FOR IMPROVEMENT. Analyst Chris Crotty with iSuppli says that as both companies improve their manufacturing efficiency and production yields, they will likely reduce the chip's cost by 20% to 25%. The same will likely apply to ATI (ATYT), which is building the graphics-processing unit, or GPU, for the Xbox. iSuppli estimates that the chip is the most expensive component in the system at $141.

And how about the cost of the Sony PlayStation 3, to be released next year?

Crotty expects that Sony's loss on the Playstation 3 may be even wider, as the cell processor that IBM, Toshiba, and Sony designed for the system is more complex.

Estimates vary as to how much the cell processor will cost. Richard Doherty of Envisioneering Group in Seaford, N.Y., expects the cell chip to cost about 50% more than the Microsoft chip. "Based on what we've seen so far, the Playstation 3 could cost as much as $600 to make in today's pricing," Doherty says.

And Crotty says that since it's a more complex chip, its price will fall more slowly than the price on the Xbox chip.

Ouch! No wonder the games cost $60 per title, to make up for the hardware losses.

Sramana Mitra on Strategy

I enjoy this blog by Sramana Mitra, who is a technology and business prognosticator. His Her blog both covers the big picture and contains nuggets of individual business/career opportunities, such as

Configuring and managing Home Networks will be a big profession, and this job cannot be outsourced as easily. A largely non-tech savvy consumer population will demand that service personnel come out to their homes and fix things. Who pays? Consumer or Carrier? Without this support, Convergence will not cross the chasm.

-- Sramana Mitra on Strategy; Blog Archive; Cisco: Inching Us to True Convergence

11/22 UPDATE: A loyal reader (from India) pointed out that Sramana is a woman, not a man. My apologies! I've corrected my wording.

ICCAD keynote | Gabe on EDA

Tets Maniwa's article (on the Gabe on EDA blog) summarizing the ICCAD keynote is a well-written overview of the Cell processor design tradeoffs.

I'm sorry I missed ICCAD; it's right here in Silicon Valley. I need to get on the right mailing list to hear about such things. It's not as practical a conference as SNUG, but it's a good resource for a look at future design technology.

EETimes.com - Alarming export: engineers

For a long time (since even I was a college student), US Engineering graduate schools have been populated primarily by foreign-born students, particularly from China, Taiwan, and India.

It used to be that such student would typically stay in the US to work. This was controversial, requiring H1B visa, and some allegations of taking American jobs or depressing wages.

Today, these students aren't necessarily sticking around. They're going back to work in their home countries, where they may be more comfortable or sense more opportunity. An example of this is described in EETimes.com - Alarming export: engineers.

Now these very bright students are taking their knowledge and work ethic back home. It's probably a net loss to the US to not have them sticking around. It shows you should be careful what you wish for!

Semiconductor Workforce Demands and Opportunities

Semiconductor Workforce Demands and Opportunities lists the specific job titles that semiconductor employers are looking for hardest.

It's an interesting list. Some of it makes sense, some doesn't. It would be best for me to look into the Analog/Mixed-Signal (AMS) field, since I'm not qualified to fill the African-American or Female Technicals openings.

Magma plans tools to address complexity challenges

Magma plans tools to address complexity challenges is an intriguing pre-announcement. What will this "thing" be?

There's always tension between wanting a "one-stop-shop" with a highly integrated environment and flow, and wanting "best of breed" tools that produce the best, fastest results. Best of breed usually wins. Getting to an integrated environment? That's what CAD departments are for. ;-)

John Cooley's DVcon'05 Trip Report

DVcon'05 Trip Report:
-or-
A Census of 338 Engineers on Design Verification Tool Use

is chock-full of EDA data painstakingly compiled by John Cooley.

It's nicely organized, and the summary at the top of each subject is well worth a read. As you get further into each article, there are a lot of one-line responses that aren't very informative, though you can get a feel for what other companies are doing.

Intel's Ultra Low-Power Process

There was a story a couple of days ago about Intel announcing an ultra-low power 65nm process. I've been looking around and couldn't find much technical detail, but New Intel 65 nm lithography promises reduced leakage for small devices at Tom's Hardware Guide has the most detail.

The power reduction is through a three-pronged attack:

1. Increasing treshold voltage. This is familiar to all nanometer-scale digital IC designers today.
2. Low Damage Junction Engineering. Uh, that's some real process engineering, and I don't have much insight.
3. Increased Gate Oxide Thickness. This is very interesting and counter to scaling and performance trends. But, when the gate oxide is only 3-5 atoms thick, you have to question "how thin is too thin?". The article just mentions making the oxide thicker. Presumably this is less risky than utilizing often-mentioned but not-in-production High-K Dielectrics.

Startup claims FPGA lead with asynchronous logic

EETimes.com - Startup claims FPGA lead with asynchronous logic one of a handful of claims for products based upon asynchronous logic design.

I'm very intrigued by this idea. It has the promise of removing lots of overhead in chips for clock distribution and balancing. Not only does all the synchronous clock overhead use a significant amity of chip area, but it uses up a large amount of the standard cell power consumption! Every one of those clock buffers toggles twice per period, giving it a "toggle factor" of 2X.

I don't recall asynchronous logic design being taught in any of my engineering classes. There need to be more resources to learn about it.

Another big roadblock is that there is not the EDA infrastructure for asynchronous design. All the commercial synthesis, timing, and test tools assume synchronous design.

Designing ICs with the 'X' Architecture

EETimes.com - Designing ICs with the 'X' Architecture is a great exposition of the emerging design style of using diagonal interconnect in addition to the traditional Manhattan (horizontal and vertical only) routing.

The good news about EDA

It is good to recognize the exciting things that our industry is accomplishing, as described in EETimes.com - The good news about EDA by Richard Goering.

I agree that SystemVerilog looks to be a better way to design and verify. It's more productive, removes some Verilog ambiguity, and has better support for formal verification.

I don't know the prospects for OpenAccess (hope it's not another CAD Framework Initiative or CHDSTD), but hope it succeeds. As Richard says, why should every startup (and every corporate CAD department) have to redevelop the infrastructure for EDA tools?

Don't know much about SystemC. Let's start using SystemVerilog first.

Intel Developer Forum August 2005 coverage

The Intel Development Forum got tons of press. Intel is running away from the "most gigahertz" school of CPU design because of the stifling problems of power management. I'll link the best articles with IDF coverage here:

• Intel Developer Forum August 2005 full coverage
• Intel abandons GHz war, embraces cool future | The Register

NVIDIA scientist calls for expanded research into parallelism

Update: this article in BYTE magazine (subscription required) describes how Intel really wants programmers to write parallel code.

This EE Times report from the Hot Chips conference, NVIDIA scientist calls for expanded research into parallelism, raises one of the "dirty little secrets" of all the hype about multi-core CPUs -- it is hard to make applications multi-threaded! Do we already have a good programming language for describing an application's parallelism, or is a new language needed?

Meanwhile, those working in the graphics arena are ideally suited to taking advantage of Moore's Law:

Kirk contrasted this situation against the entirely different structure inside the GPU. "Graphics has been called embarrassingly parallel," he said. "In effect, each stage in our pipeline, each vertex in the scene and each pixel in the image is independent. And we have put a lot of effort into not concealing this parallelism with programming."

This allows a GPU developer to simply add more vertex processors and shading engines to handle more vertices and more pixels in parallel, as process technology allows. "We are limited by chip area, not by parallelism," Kirk observed.

Xbox 360 Die Photos

Ever wonder what's in the chips that power the most powerful game consoles? Well, Xbox 360: New Tech Specs Details Surface - Xbox has die photos of both the CPU and GPU for you to oogle.

Each of these contains more transistors than an AMD Atlon64 CPU. There is a lot of power (both computing and electrical) in these chips!

EDA pioneer takes startup to new routing ground

EDA pioneer takes startup to new routing ground is a nice glimpse of this history of John Cooper, an old-time EDA guru, and looks to the future at a new type of router that his startup is developing.

I like the article more for this history than any insight I have into their new router's prospects. Also very impressive is the amount of money that Cadence paid to acquire CCT. It would be really interesting to do an analysis of what EDA vendors have paid for acquisition, and what returns they got. How about Cadence's acquisitions of Ambit and HLD Systems? HLD in particular didn't see to last long.

The Dangers of Living with an X (Bugs Hidden in your Verilog)

The Dangers of Living with an X (Bugs Hidden in your Verilog) is a technical paper that is important for ASIC design and verification engineers. It's an exhaustive analysis of interpretation of the 'X' value in Verilog HDL. This detail is often misunderstood and can be dangerous in design. The paper was originally presented at SNUG. It says the author won the Technical Committee award. I'm surprised he didn't win additional awards -- it's one of the best ASIC design papers I've read.

Constructing the next transistor

Constructing the next transistor , in EE Times, is a superb article describing the technical challenges to building useful transistors below 65nm. It covers the physical and materials challenges that are arising, and how the solution to one problem (e.g., low leakage power) may aggravate another (high performance).

I'd love to have seen this illustrated with some pictures -- I wonder if the print edition has that? In any case, if you're a semiconductor engineer or scientist, you'll find this article worthwhile.

Why, it even makes me want to dust off my semiconductor textbooks to remember what's really going on inside a MOS transistor!

EDA Vendor Earnings Announcements

I admit I'm not a financial guru, but trounces seems like a strong word for "Cadence recognized net income of just $500,000, or $0.00 per share"!

UPDATE: Synopsys will announce their 3Q2005 earnings on August 17.

• Cadence Trounces Guidance Again
• Magma Reports Fiscal Q1 Sales Up 8% The fourth largest EDA tool supplier reported record high revenue of nearly $39 million for the fiscal quarter ended July 3.
• Mentor Q2 Sales, Earnings Fall Due to lower than expected bookings, the third largest EDA player saw both revenue and earnings per share fall, but remains positive for future growth for new and emerging products.

CDNLive! Conference

Cadence's answer to SNUG, the Synopsys User Group, is CDNLive! The schedule looks pretty good -- interesting and relevant. Looks like they also managed to get customers to present their advanced product experiences rather than relying on their own marketing pitches. If you're interested, early registration discount ends on August 12.

Improving yield in RTL-to-GDSII flows

I'm very curious about how front-end or RTL design can influence manufacturability or yield in a Standard Cell flow. I don't see the connection.

Improving yield in RTL-to-GDSII flows sounds like it would explain it all for me, but the connection to RTL design still seems to be missing. I see where synthesis might be able to select cells out of a "high yield" library (if such a beast existed), and certainly there are things to do during routing, such as adding redundant vias. But this is all physical design. Is the logic designer off the hook?

A Plethora of White Papers

Magma Design Automation, Inc. - White Papers lists a number of relevant and well-written White Papers, including non Magma-specific topics such as

• Signal Integrity
• Visualizing the behavior of Logic Synthesis algorithms

Some of the other papers are more oriented to Magma tool capabilities, but because their tool suite is modern and novel, they should be informative as well.

Designing for New Dimensions

This is very "researchy" stuff, but it could dramatically reduce interconnect length, much better even than "X Architecture". Designing for New Dimensions refers to the third dimension, previously unexploited in IC design. And a picture is worth 10^3 words:

Retrospective on DAC and EDA

Ditchin' DAC is a long-time DAC veteran's take on the evolution of the Design Automation Conference, from the beginnings as a clearinghouse of Corporate CAD developments, through the booming tradeshow of the 1990s, to now, where some question whether DAC is worth the cost and time. I'm on the fence. I'd go to DAC if it were local, but usually can't justify the time and expense to travel there. DAC hasn't been in the Bay Area in several years, although we probably have the greatest number of industry customers.

Tenzing Norgay Interoperability Achievement Award?

This has long struck me as the most incongruous award in our industry: ARM Recipient of Synopsys Fifth Annual Tenzing Norgay Interoperability Achievement Award. Yes, I know who Tenzing Norgay is, but the connection to EDA??? It reminds me so much of Apple using pictures of Einstein and Gandhi to promote their products.

Interoperability plays a key role in elevating designers to a higher level of productivity, just as Tenzing Norgay's efforts facilitated the first ascent to the top of Mount Everest, said Rich Goldman, vice president, Strategic Alliance at Synopsys.

Ah, it all makes sense now. ;-)

Hot Chips' Conference Preview

EETimes.com - Hot Chips' message: It's the bandwidth gives a head-up as to the themes to be presented at the August Hot Chips conference. The top problems designers face are

1. Managing power
2. Managing the memory bandwidth bottleneck

Here for the foreseeable future is a world of parallelism, of increasingly application-directed architectures and of an unending struggle for memory bandwidth rather than Mips.

The RISC that did not pay off

EETimes.com - The RISC that did not pay off points out that while Reduced Instruction Set Computing was the rage starting in the 1980s, the reasons for its appeal are no longer dominant. Memory bandwidth has become a huge bottleneck, which wasn't the case when RISC was on the ascent.

LSI Logic RapidChip & Structured ASIC

I've always been intrigued by initiatives to bring down the ever-increasing cost of nanometer-scale IC design. While mask sets can cost more than $1M, I fondly remember the days of Gate Array vendors' ability to turn prootypes in less than a week! LSI Logic's Leverage reads like a PR piece written by LSI Logic about RapidChip, their Structured ASIC product. While intrigued, I want to understand about these technologies:

1. How do they know what IP to diffuse onto the base layers? How do you reconcile if one customer wants N Serdes macros, and another wants M megabits of RAM?
2. Who is really using Structured ASIC? How real is it, and for what applications?

Sequence CoolPower: SoC Power and Voltage Drop Optimization

Sequence CoolPower First with Comprehensive SoC Power and Voltage Drop Optimization; New Automated MTCMOS Power Gating Slashes Leakage up to 100X, CoolPower Reduces Voltage Drop Significantly with No Timing/SI Penalty is in the running for the longest-titled Press Release! The march toward low-power methodologies continues. While Vth optimization is localized and has few side effects, emerging techniques such as Power Gating have implications for design, verification, and implementation methdologies. I don't know how cleanly this works yet. Sequence is announcing a product to support this, and I imagine the big EDA players will address this as well. BTW, Sequence neglected to define MTCMOS. It stands for Multi-Threshold CMOS. The idea is that the regular functional transistors are low-threshold (high-speed, high leakage), but the power to these transistors is gated by a high-threshold transistor during non-operation or "sleep".

Discovering Multi-Core: Extending the Benefits of Moore's Law is a well-written laymen's description of the challenges to Moore's Law as we face physical limits in scaling chips.

• The argument for "scaling out" is similar to NVIDIA's SLI strategy, which links two GPUs to work in parallel on graphics rendering.

Reflections on DAC

Reflections on DAC by Gabe Moretti is an good overview of this year's Design Automation Conference. Other than his tedious attempt to define a new taxonomy for the EDA market, I enjoyed his observations about the show and analysis of the big EDA vendors.

Sony May Lose Up to $1.18 Billion on PlayStation 3 – Merrill Lynch

Sony May Lose Up to $1.18 Billion on PlayStation 3 – Merrill Lynch is an interesting analysis of the economics of game console hardware. ... estimates that the machine’s main components – namely its Cell chip, NVIDIA RSX graphics processor and BD-ROM drive – will cost about $101 each. Oh well, they will sell a lot of $50 game CDs to recoup the hardware cost!

Do we have a brain balance deficit?

EDA analyst Gabe Moretti has written an insightful analysis of offshoring and issues facing engineers in particular. Take a gander at Do we have a brain balance deficit?. I agree that H-1B workers are better for the US than offshore outsourcing! I also relate to his observations on why an engineering career isn't as attractive as medicine or law.

Delay of ATI R520 to boost Nvidia 4Q sales

An interesting explanation inDelay of ATI R520 to boost Nvidia 4Q sales: the company is facing leakage issues, as it attempts to migrates its manufacturing to a 90nm process It is rare to see such a specific attribution of production problems! I wonder what techniques they are using and what's not working? Vth optimization? Power Gating? ...

EDA startups tout more nimble physical design

Startups at DAC fielding interesting new products were covered in EETimes.com - Three tout more nimble physical design

• Magma's Quart-DRC high-performance distributed DRC.
• Apache PsiWinder critical-path and clock tree analysis tool that considers crosstalk and dynamic-power integrity effects.
• Sierra Pinnacle physical-synthesis tool to concurrently optimize timing, area, power and signal integrity across all operating modes and corners.

Xbox 360 unlikely to outsell PS3

This story describes a detailed market analysis for next-generation game consoles. It's very hard to predict how things will play out, but from the sound of it, I'm glad that Sony and NVIDIA are together for the PS3.

ATI, Cadence and TSMC Produce X Architecture Chip

The X Architecture initiative, an early example of which is described in ATI, Cadence and TSMC Produce Industry's First Fabless X Architecture Chip, is based on a straightforward idea: rather than run all the wires on an IC horizontally and vertically (Manhattan routing), devote a couple of layers to routing diagonally at 45 and 135 degrees. It allows you to "cut the corner" and routing distances become shorter. I think the biggest challenges to making this work are on the manufacturing side, which is why there's been heavy involvement from foundries like TSMC and semiconductor equipment manufacturers. I first heard about the X Initiative when Simplex Solutions and Toshiba were working on it several years ago. Cadence acquired Simplex, and this technology is starting to be introduced commercially now. UPDATE: This article has more technical detail.

TSMC Reference Flow 6.0

TSMC issued a press release to announce their Reference Flow 6.0. It emphasizes (1) low-power design, including building blocks for a "power gating" methodology, and (2) Design For Manufacturing. It's also interesting that TSMC's trend is to integrate more value-add rather than be a 100% pure manufacturer. For example, TSMC is offering their own libraries for standard cells, memories, and I/O. It may be that this is natural, given the increasing relationship between Design and Manufacturing. But it should also help their business margins as they add more value. UPDATE: EETimes.com - TSMC reference flow heralds 65-nm transition

ChipEstimate.com

ChipEstimate.com is a very interesting concept to help a chip management team "size up" a proposed IC. Based on high-level information about gate count and IP used, it comes up with a floorplan and, at an additional cost, will provide budget estimates for manufacturing the chip with various foundries' processes. I remember that eSilicon had a similar budgeter, though it was intended for designs to be done with eSilicon. This ChipEstimate.com appears to be a standalone estimation product.

Design for Manufacturing: What Designers Need to Know About the Change in Yield Management

I've been reading this paper, Design for Manufacturing: What Designers Need to Know About the Change in Yield Management, at lunchtime, and find it to be an excellent overview of all the "DFM" effects that you hear about. Antenna effects, need for metal fill, what's wrong with Copper, are all topics that are covered in an introductory way. Nice starter!

IBM markets statistical timing analyzer

EETimes.com - IBM markets statistical timing analyzer announces IBM's (re-)entry into the commercial EDA market. "Statistical STA" is new and hot. It should allow for less pessimistic STA, which becomes a critical requirement around 65nm. If you guardband to assume that every parameter is 3-sigma worst case, that's an unrealistic situation. A Statistical STA tool would understand that what combination of variations would happen with 3-sigma probability. Magma plans to launch a tool, but I haven't seen Synopsys or Cadence announce anything. Another type of variation is "location-based correlation". I don't see that addressed by the IBM STA tool.

Xbox 360 GPU Details

Xbox 360 GPU Details goes into some detail about ATI's GPU for the next Microsoft console. What's particularly interesting and impressive are the efficiency claims and the use of embedded DRAM.

E3: Game Console Wars and Booth Babes

E3: Game Console Wars and Booth Babes provides a very good overview and comparison of the next-generation gaming consoles. As for the ultimate winner, it's way to early to know. But the article does take Sony to task for showing too much "smoke and mirrors", whereas Microsoft is showing real development. You have to read all the way to the end to see the "Booth Babes", but they are in there! Nothing like any conference I've ever been sent to!

Line blurs between graphics IC and CPU

I've been wondering about the role of the NVIDIA GPU vs. the Cell processor in Sony's Playstation 3, and this article explores some of the tradeoff possibilities. Both chips can do high-powered vector processing. Apparently the Xbox 360 and ATI GPU have similar opportunities for sharing the workload. The ATI multi-die packaging is unique. (Is that good or bad?)

SYNTHESIS:'Topological' tool improves postlayout timing, area

This could be a welcome breakthrough by Synopsys Design Compiler: 'Topological' tool improves postlayout timing, area. Also, see the Synopsys Press Release. It isn't new to include placement with synthesis (that's what Physical Synthesis is), but if they include this in DC-Ultra logic synthesis, it's easy to use, and it correlates to Layout, then that's a big win.

Console Wars! Playstation 3 doubles Xbox 360 performance

It's going to be interesting watching the next generation of game consoles come out next year. All three vendors provided previews of their systems in the last week, see EETimes.com - Playstation 3 doubles Xbox 360 performance. It's exciting the NVIDIA is partnered with such a successful leader in Sony. There is some description of the NVIDIA "RSX" graphics chip in the article. Onward! Update: PlayStation 3 stats spotlighted

Silicon Design Systems Delivers Next-Generation Router

Silicon Design Systems Delivers Next-Generation Router. Well, it is a press release, but it certainly sounds like a novel routing approach. Would be interesting to learn more. Also novel is the company's heritage: originally a design services firm, they've now decided to develop EDA tools. Although EDA can be a small market, there's potential for higher margins (and possible acquisition) that company's can't enjoy as a "services" firm.

Atrenta RTL Analysis Products

I've become interested in RTL checking (linting) tools, and Atrenta has one of the most comprehensive offerings. They have introduced a new set of products (some repackaged from SpyGlass) and the new product family is called "1Team". 1Team:Analyze 1Team:Verify SpyGlass� Constraints Demonstration Update: In addition to the above company press releases, here's an overview by Richard Goering @ EE Times. EETimes.com - VERIFICATION: Atrenta adds analysis to suite of 'predictive' tools

Toshiba Demonstrates Cell Microprocessor Simultaneously Decoding 48 MPEG-2 Streams

On of the most-hyped chips on the horizon is the Sony/Toshiba/IBM Cell Microprocessor. Will it render today's microprocessors and graphic chips obsolete? It is slated to go into Sony's Playstation 3 (along with an NVIDIA GPU) and also many other consumer electronics applications. An early demonstration of the chip is reported in Toshiba Demonstrates Cell Microprocessor Simultaneously Decoding 48 MPEG-2 Streams -- Tech-On!. Especially interesting is the interview linked at the bottom with Sony's "Father of the Cell Chip".