Engineering Halloween

He only pokes fun at Marketing a little bit this time.

I must confess, I once dressed as an integrated circuit for Halloween. It was in college and I was a DIP. Maybe that's why it didn't impress the girls? Have a great weekend.

Are You Listening?

When I'm out and about doing chores or exercising, chances are I'll be listening to my iPod. But more often than not, I'm listening to podcasts rather than music. Listening to podcasts is an efficient way of "reading on the go". You can catch up on the latest news stories, political opinions, or investment ideas. Those are my interests; you can find a podcast on practically any topic.

Have you listened to podcasts? Which are your favorites? In our field of semiconductor engineering, there's not a wealth of content. But here are some of my favorite engineering/technology podcasts to get you started.

1. IEEE Spectrum Podcast, which is described at Podcast Picks.
2. Science Friday by Ira Flatow. A classic high-quality program from NPR.
3. Security Now by Steve Gibson and Leo Laporte. It's mainly about computer security, but you can also learn the latest on PC software and networking by listening.

It's easiest to subscribe through iTunes, but there are other ways using the RSS feed and a "podcast catcher" program. Happy listening!

Synopsys Users' Group CFP

As you may have heard me say (write) before, the Synopsys Users' Group (SNUG) conference is the most useful conference I attend each year. If you're involved in chip design and haven't attended, you really need to check it out. There are conferences around the world, but the biggest one is in Silicon Valley every March.

Why am I bringing this up now? Because the Synopsys Users Group - San Jose Call for Papers is open! Here's a chance to show your chops and burnish your resume by demonstrating the cool stuff you're doing with Synopsys tools. The authors get a lot of support from the experience Technical Committee [full disclosure: I'm a member] to help develop their presentations and papers. Think about it, and I'll see you at SNUG.

Career Thoughts

Image courtesy Wikimedia.

Taking a break from the technical, career issues merit reflection and discussion. Here are some brief thoughts.

How's the Market?

What's your perception of the ASIC/EDA jobs market? My take is that it's pretty weak, but a number of companies are "selectively hiring". I had a couple of friends leave their struggling design services firm, and they were able to land jobs at established growing companies within a couple of months. On the other hand, there are plenty of engineers who have been looking for many months.

One differentiator is that hiring favors leading-edge experience (e.g., expert P&R and design closure of 65 or 45nm chips), or knowledge (e.g., advanced degree with an emphasis on an emerging hot area).

Natives Say No

With the depressed job market, this isn't the best time to wonder about this, but I'm perplexed at the lack of US-born chip design engineers. Of course, it stems from the lack of US-born engineering graduates. This leaves me scratching my head--engineering jobs are not THAT bad. As a matter of fact, they're one of the fastest ways to earn a very good paycheck out of college, with intellectual challenge to boot.

A downside is that engineering isn't the most secure career around. There are regular risks of downsizing or technological obsolescence. It's not a cushy career, but how many are in this age of globalization?

If you want a secure career, at least medicine and law are "less outsourcable". However, if you really want societal respect, security, and a guaranteed comfortable retirement, I recommend becoming a fireman.

Give US Your Best and Brightest

In the US, we are so fortunate to attract many of the best and brightest scientists and engineers from the rest of the world. There can be complaints about "H-1B abuse", but there needs to be a system that allows the country to benefit from the great contributions possible from immigrants with advanced degrees.

Where Do Seasoned Engineers Go?

While I'm not there yet, friends and I do wonder where all the full-career engineers are. Look around you -- do you see many 50-something engineers? I don't, and I wonder. Do they all transform into real estate agents? Or should I worry about a future as a Walmart greeter?

Others Weigh In

1. As I was preparing this post, a timely and provocative article appeared in EE Times, U.S. engineers at a disadvantage . The discussion in the comments is fascinating.
2. Update: Harry the ASIC Guy and his commenters weigh in on outsourcing, and IBM's aggressive program in particular.
3. Update: Lou Covey has analysis and advice at We're in this boat together. Start acting like it.

Everybody's Getting Physical

Image courtesy Wikimedia.

Back before "nanometer design", there was "deep submicron design", and ASIC synthesis users became very concerned about interconnect effects on timing. The first attempt to deal with this was through "Links to Layout", and especially a whole slew of custom wireload model (CWLM) strategies. If you look at SNUG programs a number of years ago, there were more CWLM papers than you could shake a stick at.

A major advance in accounting for interconnect effects was when synthesis tools started to perform "virtual layout" as part of the optimization-estimation-timing analysis loop. The most notable tool to do this was Synopsys Design Compiler Topographical. My colleagues and I did evaluations of DCT starting with 90nm designs, and data indicated better correlation and generally a better netlist for Place & Route.

As we progress from 90nm to 45nm and below, physical considerations are becoming ever more sophisticated. The latest examples are

• Synopsys Design Compiler Graphical. Includes congestion prediction and some congestion relief algorithms.
• Cadence RTL Compiler's New "Spatial Technology", the latest physically-aware RC feature.
• Oasys RealTime Designer. "RTL physical synthesis."

The Skeptic Weighs In

While "getting physical" has the feeling of more accuracy and general goodness, TNSTAAFL. Though I hope for better quality of results and predictability, I see the following drawbacks

• It forces the logic designer to learn physical design details, and learn new tools or coordinate with a physical designer. While that's nice to know, it takes away from the RTL creator's time to focus on architecture, design and verification.
• The optimization process itself will either take longer (to perform the "virtual layout"), or results will be less-optimal, because optimization time will be taken away in order to run physical algorithms.
• Some of the effort may be wasted, especially for detailed buffering and gate sizing. For example, some P&R tools "throw away" the incoming netlist's buffering and sizing, and re-optimize in the physical domain. So, that effort in logic synthesis is wasted (other than its predictive benefit).
• While WLM-based synthesis is well understood and mature, these physical tools are not. It may take a long refinement period for the tools to produce reliable netlist quality and consistency.
• Some of these tools can't decide if they're logic design tools, physical design tools, or some mish-mash of both. In their efforts to be accessible and affordable for logic designers, they may lack the physical design functions and data access needed to do the job right.

Over the coming months, advanced synthesis users will be putting these latest tools through their paces with real designs. And we'll start to learn whether the added complexity and cost leads to better implemented designs. If not, we can always go back to our old friend the wireload model, trying to get to P&R quickly, where the rubber really (not virtually) meets the road.

Update: I stumbled upon a detailed reply/rebuttal over on the Cadence Logic Design blog! Jeffrey Flieder, thanks for writing this. I very nearly overlooked it.

Found at DAC

My pre-DAC post Looking Forward to DAC laid out what I hoped to investigate by visiting exhibitors, namely

• Low Power
• Datapath
• MCMM
• parallelism
• Asynchronous Design

Well, despite my best-laid plans, I wasn't able to check all these items on my list in two days of roaming the exhibits floor. In some cases (i.e., Asynchronous Design), I didn't find an appropriate vendor. In other cases, my schedule or the vendor's appointment constraints didn't allow me to gather the information. But DAC was a great opportunity to see many vendors, and by careful plan or happy accident, I was able to visit many interesting companies. I'll group my vendor impressions into these categories:

High-Performance Design

• It seemed like Oasys Design Systems was the most talked-about implementation vendor at the show. As I've said before, their capacity and run time claims are incredible. At this show, they put a lot of emphasis on making their claims credible. They've got some customer testimonials to validate them, and their closed-door demo suite explains what's revolutionary about their physical synthesis approach, and why it could be dramatically faster than today's synthesis tools. Update: Harry the ASIC Guy explains technical details of Oasys' approach.

  And to top it all off, I just about ran into Joe Costello on the DAC floor. (He was suspiciously near the Synopsys booth at the time.) It should be great to have Joe back in the EDA industry. I like and respect Aart de Geus a great deal, but Joe Costello can add motivation and excitement back to an industry that's feeling tired.

• Micro Magic is an interesting small design/tools company that's been around almost 15 years. Because DAC wasn't very crowded on Wednesday, I could walk into their booth and have a long informal chat with their CEO. He exudes confidence and credibility.

  One of their tools is a Datapath Compiler, which is one of the few commercial solutions for maximum performance datapath design. Other companies have come and gone (Arcadia is long gone; Arithmatica wasn't at DAC), but Micro Magic apparently has numerous real success stories. (Their customers seldom allow themselves to be named.)

• iNoCs is an early stage startup with tools to synthesize Network on Chip (NoC) IP. Their debut was especially timely because NoC was one of the technologies featured in the Wednesday Keynote by Bill Dally, Stanford professor and NVIDIA Chief Scientist. As it turns out, the connection is even stronger. iNoCs is advised by noted EDA professor Giovanni De Micheli, who has been a colleague of Professor Dally.

Parallelism

• The only company I met with a heavy focus on new parallel computing products was ACCIT, which is developing highly accelerated SPICE simulators running on ATI GPUs. Looking forward to the NVIDIA CUDA port, guys!
• Of course, many of the big EDA vendors are adapting their products for multi-core technology, for example Synopsys PrimeTime Multicore.

ESL Synthesis

I spoke to a few vendors in this space, but I wouldn't dare pretend to have a good grasp on where the field is at. Several journalists and bloggers are writing "now is the time for ESL synthesis", but I have yet to meet the designers using it or even enthusiastic to get into it. It's puzzling to me. There apparently are specific domains with considerable success, such as wireless and image or video processing. And there are specific geographic areas adopting it first, namely Japan. But for the mainstream ASIC designer, I don't yet see it catching on.

Others

I liked what I heard in a brief visit with Imera, which develops hardware+software solutions to allow secure remote debug of software (e.g. EDA tools). In my work, there is constant antagonism between the EDA vendor, whose engineers claims they cannot debug their software beyond their walls versus the EDA customer, which doesn't want the "company jewels" of full-chip RTL or netlists to ftp over to the EDA vendor. Imera has solved the problem with a distributed debugger and networking solution that allows the R&D engineer to debug from the vendor side, while the EDA tool is running on the design data at the customer's site. Sounds like it would resolve the stalemate and allow us to get on with the problem-solving.

Overall Impressions

I had not attended DAC since 2006. It was a little disorienting because of all the changes in the industry and the conference itself. Attendance was way down from boom times. For the first time, I had an "exhibits only" pass, which allowed me to go up every day and visit the exhibits floor but not the technical program. After Free Monday, the floor was much less crowded, and it was a pleasure to walk right up to any vendor and get all my questions answered. One irritating practice of several vendors was to not have any open demos, but to require a one-hour appointment to be scheduled for a closed-door meeting. I found this quite inconvenient for any sort of spontaneous discovery, and as a result both vendors and I missed out on some worthwhile discussions.

I was glad I attended DAC. I obtained information that will help me in my job, and met old and new friends. I wish for the sake of the organizers and the exhibitors that attendance had been stronger, but the economy was a strong tide to fight. Let's hope that tide is turning and the 47th DAC in Anaheim will celebrate a growing vital EDA industry.

DAC Meta-Blogging

If you're at DAC and haven't yet overdosed on "Social Media", please stop by Tweet, Blog or News: How Do I Stay Current? this afternoon. I'll be on the panel, sharing ideas for how to wade into this trend in the most efficient way. Listen, ask questions, and say Hi.

Denali Software is a great supporter of DAC. They teamed up with Atrenta and Springsoft to start the I Love DAC program and provide dozens of complimentary Exhibits passes for the conference. They also ran good-natured competitions for EDA's Next Top Blogger and EDA's Community Superheroes. Congratulations to Karen Bartleson of Synopsys for winning the Top Blogger distinction, and Joy Matsumoto from Cadence for her great efforts to support charitable causes.

The Road Less Traveled

DAC begins its second full day in San Francisco, and I encourage you to take advantage of the opportunity. I was up there yesterday and found a great variety of vendors, panels, and other events to check out. In the morning, crowds were pretty sparse, but there was a definite pick-up in the afternoon. In particular, there was a lot of congestion around the prominent Synopsys booth, next to a well-visited Standards area.

Fellow blogger JL Gray in front of Twitter Tower (image courtesy jlgray)

Synopsys is diving into "Social Media" in a big way at DAC, so it's worth checking out Conversation Central with its variety of sessions on how to understand and make the best use of these new communications media. The Twitter Tower is a novel way to take in DAC's zeitgeist.

That said, I'd encourage everyone to venture out beyond the comfort and safety of the big EDA vendors! If anything, I de-emphasize visits to the top vendors, because one can follow their announcements and arrange meetings any time of the year. But DAC is a unique opportunity to see a great variety of vendors, from the "second tier" specialist that you're not quite familiar with to the Mom & Pop startup that just rolled out their shingle for their first DAC. To make this discovery more purposeful, I flip through the Exhibitor descriptions in the DAC program and highlight the booths of companies that sound remotely interesting. That way, you can avoid wasting time by ping-ponging between North and South halls. Go for it!

On a lighter note, on Sunday I made my way to San Francisco for an EDAC reception. Before that, I explored Golden Gate Park (stunning!) and snapped a few pictures.

The first perplexed tool user.

Real-Time DAC Tweets

The next best thing to being at DAC is to watch the "tweets" posted by attendees--

Getting to DAC

There has been no end of posts about "going to DAC", what to see, what's hot, etc. But, how to actually get to the venue? Since I'll be making the trek solo from Silicon Valley and am phobic about the hassle and expense of driving and parking in SF, I'll share some public transportation research.

Caltrain

Caltrain provides service on the San Francisco Peninsula. Here's their schedule. If you catch one of the "baby bullet" express trains, it's less than an hour from San Jose to San Francisco. Fares from San Jose are

One Way	$7.75
Day Pass	$15.50

From the Caltrain station in San Francisco, you'll need to get to Moscone Center. In previous years, DAC ran a shuttle for this, but I don't see any notice of it this year. You can either walk or take the city bus. It's only a one-mile walk, so I plan to try this and count the back and forth as my exercise for the week. Google has a nice map showing both the walking route and links to bus schedules, if you prefer. View Larger Map

BART

Bay Area Rapid Transit has stations on the Peninsula and East Bay (Fremont is nearest to Silicon Valley) and can take you to Montgomery Station, only 3.5 blocks from Moscone Center. The One Way fair from Fremont to Montgomery Street is $5.60.

Synthesis Gets Interesting

As a pleasant surprise, there's quite a bit of activity and emerging excitement in the area of synthesis, just in time for this year's DAC.

Physical Synthesis

Oasys Design Systems has come out of stealth mode with rather incredible performance claims.

It's exciting to hope for a revolution in synthesis. Put me in the "show-me" camp. It's (relatively) easy to meet 80% of what Design Compiler can do, but there are many features and tricks developed by DC over the years, making it a hard tool to displace. Synopsys has certainly seen strong competition, including from Ambit BuildGates (acquired by Cadence) and most recently by Get2Chip (now Cadence RTL Compiler). What often happens is not that king DC is overthrown, but that the competition lights a fire under Synopsys and their tools will improve at a much faster pace than market dominance would dictate.

What's interesting about Oasys are the tremendous claims about capacity and run time, and the emphasis on physical synthesis, combining logic synthesis with placement and optimization. The company also has impressive board members, including Sanjiv Kaul (former implementation GM at Synopsys) and, re-appearing to EDA after a long hiatus, Joe Costello (charismatic and successful former Cadence CEO).

ESL Synthesis

For several years, EDA industry analyst Gary Smith has been calling for the ascent of ESL (Electronic System Level) design. He was already called an ESL evangelist back in 2006! It's been the next big thing for a while now. It seems to follow the industry's progression from transistors to gates to RTL, but RTL remains the mainstream design method.

In the context of design implementation, ESL implies synthesis at a more abstract level than RTL. This year, there appears to be considerably more buzz, and not just from Gary. See, for example, recent posts by John Cooley and Richard Goering.

Key players include

• Forte Cynthesizer
• Mentor/synthesis CatapultC
• Cadence C-to-Silicon
• Bluespec
• Synfora Pico Extreme

My apologies for any I've overlooked--I'm learning about this field. One point of concern is that there isn't a consensus on design language/dialect, which varies by vendor over C, C++, SystemC, and proprietary languages/extensions. That can impede adoption. It was Design Compiler that established the de facto standard for Verilog RTL synthesis subset, and this provided a common point for customers (and competitors) to converge on.

It's nice to see continued innovation in this critical area of IC design, and merits further investigation.

Looking Forward to DAC

As most everyone is aware, the big conference in the chip design software world, DAC, runs July 26-31 in San Francisco. I'm looking forward to it and plan to be up there most days. Some prognosticators have posted their "must-see" lists. (Gary Smith, John Cooley laying out the law for aspiring vendors) and there will be more to come.

Rather than calling out specific companies, I'll share some of technologies that I'll be looking to learn more about.

Low Power

This is one of the genuinely valuable and necessary "next big things" in methodology.

Datapath

I've always been surprised that specialized datapath techniques aren't more successful. It seems like you either use an advanced RTL synthesis tool, or design datapath by hand. There's not a lot of in-between.

MCMM (Multi-Corner, Multi-Mode)

It sounds like the solution to many problems. But how well does it really work -- how scalable is it?

parallelism, multi-threaded, multi-core, GPGPU

How will EDA ever catch up to designs scaling by Moore's Law? By using the parallelism available in today's CPUs and GPUs. Multi-core is working today for 4-8 cores, but may hit a wall beyond this. And what about the tremendous parallel computational power in your Graphics Processing Unit? A few EDA tools are leveraging the CUDA platform; where will it pop up next?

Update: check out Richard Goering's interview with EDA luminary Kurt Keutzer on this topic.

Asynchronous Design

This is my token research-y interest. Synchronous design is what we all learn in school, and there's a plethora of tools (namely, the EDA industry) to automate such designs. But there are drawbacks with respect to area and power. Can we learn a new way to design, and develop new sets of IP and automation tools?

You Probably Believe We've Landed on the Moon, too

Don't believe everything you read. There's an insightful behind the scenes exposé on DeepChip about a technology web site that turns out to be a marketing venue for a group of EDA start-ups. Nothing wrong with that, but the disclosure of who's behind it took some digging and questioning to tease out.

Of course, one would be naive to assume this doesn't happen elsewhere in the media. Even Mr. Cooley's beloved DeepChip, with its purported user-generated content, can be gamed. When you read a glowing endorsement of an EDA tool, ask yourself questions such as

• Who wrote this? Are they "anon"?
• Did they really write it? Or could it have been "ghost written" by the EDA vendor and submitted in the customer's name?
• What is the author's interest in the vendor? Does the author's company have a financial or other interest in the vendor's success?

Nothing beats the testimonial of someone you know and trust, other than your own hands-on evaluation.

p.s. in honor of Apollo 11's 40th anniversary, read more about Apollo Moon landing hoax conspiracy theories .

DAC Appeals to Users

When I first started attending DAC (1990 in Orlando), as an ASIC designer who'd recently joined an EDA group, I found it disorienting. The exhibits floor seemed like a circus with attendees rushing from one booth to the next to collect the best schwag (some things never change). I dutifully sat in paper presentations that sounded interesting, but I soon realized they weren't addressed to designers or users. I came to think of them as "PhD theses showing a routing algorithm that performed 13% better on an academic benchmark". Not to belittle those papers -- the mathematics and rigor impresses me greatly, but I don't understand all of it or apply it in my job.

Over the years, DAC has become more user friendly. The panels in particular are often informative and sometimes provocative. I find that I'm getting more and more out of DAC.

This year, there's an explicit "User Track" at the conference. I'd like to share a description of the User Track while presenting the first guest post on John's Semi-Blog. Please enjoy!

User Track at DAC:  Learn from Your Peers

Soha Hassoun
Tufts University
46th DAC Design Community Chair

Leon Stok
IBM
46th DAC New Initiatives Chair

Today’s connected world makes it possible for you to work from everywhere.  Yet, there’s only one place where you can learn how your peers successfully applied design tools to chip design and where you can exchange valuable experiences:  the new User Track at this year’s DAC.

The three-day User Track features 40 presentations that run in parallel with regular technical sessions.  Speakers include expert designers from Cisco, ClueLogic, Fujitsu, IBM, Infineon, Intel, Qualcomm, Samsung, STMicroelectronics, Sun, Texas Instruments, Virtutech, Xilinx and others.

Identifying Front-End Challenges

Power planning and verification continues to be hot.  A team from NEC will detail an automated flow to pre-characterize the power consumption of a set of basic components starting from their behavioral description in C, down to their power estimation at the gate-level netlist.  A team from Cisco will describe the use of a power noise analysis tool to analyze system power integrity.  Engineers from Texas Instruments will illustrate how they used an EDA tool to integrate complex multi-power/voltage domain design.  Intel engineers will present a flexible, high-level power management modeling and simulation framework for power architects.  And, a team from STMicroelectronics and ST-Ericsson will outline an exploratory and refinement-based power planning system.  Also, Intel engineers from India and Israel will offer a novel direction for using abstract executable models to verify power management protocols.

Tackling Backend Challenges:

In the Practical Physical Design session, a team from Intel will discuss how they tackle ECOs as late logic changes delay the process and register arrays occupy more than half of all transistors of modern designs.  Qualcomm designers will describe how they build their semi-custom methodology and STMicroelectronics engineers will outline e how they use the IP-XACT standard from Spirit to enable IP reuse.

Accurate power supply and substrate noise analysis remains a challenge, and practitioners from Qualcomm, IBM, Samsung and Kobe University will show how they attack the problem.  Texas Instrument designers will show how to analyze blocks for reuse in multiple metal stacks.  Intel engineers will highlight their approach to assessing design feasibility early in the process to avoid problems later.

A team from Stanford University, Rambus and Netlogic describes a way to tackle analog reuse as it becomes as important as reuse is in digital design.  A group from Cadence and several Taiwanese universities will describe their approach to integrate MEMs in mixed-signal designs.  Engineers from NXP and Magwel tackled the problem of analyzing substrate noise and will present their results in 90nm process technology.  With complex circuits often needing an integrated approach to physical and electrical verification, a team from SysDsoft and Mentor describes how they accomplished this on their designs.

In addition, join us for an Ice Cream Social Wednesday from 1:30pm-3pm where 42 posters will offer an opportunity for you to mingle with other EDA tool users. 

Access to the User Track is included with the full-conference registration.  Or, register separately for the User Track and get access to the keynotes, in addition to the User Track.  For more details, visit:  www.dac.com.  We look forward to seeing you in San Francisco.

###

For more information:

Nanette Collins

Publicity Chair, 46th DAC

(617) 437-1822

nanette@nvc.com

The Year DAC Changed Forever

There is so much good DAC material coming out; EDA is hitting critical mass in the blogosphere. There's a new social network site "I Love DAC" that ramping up, where I was delighted to see this flashback from the heydey of EDA: 1991: The Year DAC Changed Forever - The DAC Fan Club. (props to Steve Leibson)

Not only is the video entertaining, but it's a bona fide piece of EDA history. It's also worthwhile to reflect on the promise of Frameworks, still unfulfilled in EDA: seamlessly integrated multi-vendor tool flows. Well, at least it's job security for CAD engineers.

Denali DAC Festivities

The EDA company Denali is famous for their DAC parties. They are also running fun contests where the public can vote for the top EDA blogger or community superhero. See some new faces and vote for your favorites at

• EDA’s Next Top Blogger
• Community Superhero

And, at the party itself, watch the show and vote for EDA Idols!

DAC Attendance Deals

According to John Cooley's DeepChip site, Atrenta, Denali and Springsoft will be sponsoring 600 free DAC Exhibit Hall passes this year.

John also posted that the very popular "Free Monday" deal is coming back as well. Here's what his email described:

From: Bob Gardner [bobg=user domain=edac.org]

Hi, John,

Please inform your readers that EDAC has decided to sponsor the return of "Free Monday" to DAC this year. If they want to take advantage of this "Free Monday" registration, your readers must go to:

http://www.deepchip.com/FreeMonday.html

and complete all four pages of the registration. On the THIRD page they'll find a newly added "Free Monday Exhibits" option -- they MUST check this box to get this special registration.

On the forth page they should see a web receipt with their unique bar code confirmation on it. They must print this entire page.

To enter the DAC Exhibit Hall on Monday, July 27th, the engineer must present a paper copy of his/her entire bar code page to the Advance Registration desk located in the North Lobby of Moscone Center.

See you at DAC, John!

- Bob Gardner EDAC San Jose, CA

As for me, I've already paid my $50 for the all-DAC exhibits pass. See you there. The buzz for DAC is heating up, so watch for more blog posts before the conference.

DAC on Sale

Just a quick reminder: DAC 46th Registration Rates go up after June 29, so register today to get the early discount. See you in San Francisco!

Sean Interviews Rajeev

Though he's not as colorful as Gerry Hsu, Rajeev Madhavan, CEO of Magma Design Automation, is one of the most interesting and outspoken executives in the EDA industry. Check out Sean Murphy's Interview with Rajeev.

Rajeev founded several significant EDA companies, was apparently out-manuvered in the board room at times, and is forthcoming with what he's learned about the EDA industry and building companies.

EDP 2009 & the Return of ASIC

Electronic Design Process 2009 Symposium Program has links to the presentations from this April workshop in Monterey. I've never gone before, but it looks relevant and interesting.

I glanced at a few presentations and was most surprised to see predictions of the resurgence of ASIC vendors (vs. today's popular "COT" model). I'm not sure I agree, but it makes a certain amount of sense. It takes a lot of tools, people, and expertise to implement 45 nanometer chips. The proposition is that if it is possible to cleanly hand off at RTL, then the chip designer can focus on functionality, and let an implementation house focus on the tricks and traps of nanometer-scale design closure. But that's a big if, to be confident that the hand-off is of a properly constrained and realizable design!