Mendence, the Merger

We have to come up with a clever name for the combination of Cadence and Mentor. Chris Edwards coined* Cadentor, which is actually a pretty decent name. Going the other way, Mendence is too close to "menace" or "mendacity", so I suppose the PR types won't buy that. (When AMD bought ATI, the irreverent press dubbed it DAAMIT.)

Cadence's unfriendly bid to acquire Mentor Graphics is red meat for the EDA blogoshpere! (Be sure to click on that link. It's a fascinating one-page summary of dozens of EDA news & opinion sources.)

I've read many thoughtful commentaries on the possibility. Frankly, most of them are unfavorable on the deal. Some of the substantial analyses:

• Can you guess Gabe's take on Cadence's arrogance?
• Chris Edwards initial take.
• Later, Chris has a very pretty picture of how the companies' main products line up at Overlaps 'r' us.
• Ron Wilson has a possible explanation (conspiracy theory?) for Cadence's motivations.

Two of the more curious quips I read:

• Customers don't want the EDA vendor to provide a complete front to back flow. They want best of breed tools, and for third party companies to link them together. I agree that we need best of breed tools, but not that we need third party companies to hook them together. Are there examples of companies that make a good business of that? That sounds like an ASIC company, and they aren't exactly thriving. There also used to be a company called Reshape that had their own physical design flow on top of commercial tools. But they ended up going out of business.
• Cadence acquiring Mentor could present a big challenge to Synopsys. Well, I don't know. When two established giants come together, what technological advance does that enable? Not much that I can see. A bigger challenge is when a giant acquires a startup with hot new technology: think Cadence with Get2Chip, or potentially Mentor with Sierra Design Automation. One successful big acquisition was Synopsys acquiring Avant! -- I don't know what went on under the covers, but the products were complementary and continued to be successful after the deal was done.

  Of course, there may be "business synergies" -- cutting common administrative and infrastructure costs, and having a bigger menu for "all you can eat" deals. But it's kind of sad if one of the biggest business events in EDA just comes down to that.

*Update: Gabe Moretti lays claim to coining "Cadentor". I'll let Chris and Gabe hash it out.

NEWS FLASH: Cadence Proposes to Acquire Mentor Graphics

And then there were three? This just in: Cadence Proposes to Acquire Mentor Graphics for $16.00 per Share in Cash.

What is Mentor good at? I haven't used their tools recently, but by reputation I think they're strong at

• DFT (FastScan)
• LVS/DRC (Calibre)
• Simulation (former ModelSim)
• Certain pieces of Place & Route (Sierra)

So, does Cadence need some or all of these pieces because they're not strong? That's certainly the case for DFT: Mentor is a leader and Cadence is an also-ran. Or are they just "buying" Mentor's customer base?

UPDATE: Other blog reactions:

• Cool Verification. A verification tools perspective.
• EDA Thoughts. No, honestly -- tell us what you really think of the merger!
• EDA Cafe. Several news releases, including Cadence's own presentation on the deal.
• Sramana Mitra on Strategy. She's been calling for a consolidation in EDA, or some kind of shakeup in the business model. Her post has a good selection of links to her previous writings on the EDA business. This post also has the best comments thread on the topic.

One More Thing: Apple to Tackle Parallel Computing

Apple in Parallel: Turning the PC World Upside Down? - Technology - New York Times Blog quotes Steve Jobs in a discussion of harnessing multi-core computing:

Apple, he asserted, has made a parallel-programming breakthrough.

It is all about the software, he said. Apple purchased a chip company, PA Semi, in April, but the heart of Snow Leopard will be about a parallel-programming technology that the company has code-named Grand Central.

“PA Semi is going to do system-on-chips for iPhones and iPods,” he said.

Grand Central will be at the heart of Snow Leopard, he said, and the shift in technology direction raises lots of fascinating questions, including what will happen to Apple’s partnership with Intel.

Snow Leopard will also tap the computing power inherent in the graphics processors that are now used in tandem with microprocessors in almost all personal and mobile computers. Mr. Jobs described a new processing standard that Apple is proposing called OpenCL (Open Compute LibraryComputing Language) which is intended to refocus graphics processors on standard computing functions.

“Basically it lets you use graphics processors to do computation,” he said. “It’s way beyond what Nvidia or anyone else has, and it’s really simple.”

Since Intel trails both Nvidia and A.M.D.’s ATI graphics processor division, it may mean that future Apple computers will look very different in terms of hardware.

Will OpenCL be an alternative to NVIDIA's Cuda software interface? Read the comments in the NY Times blog for some good technical analysis and the usual passion that surrounds any Apple pronouncement.

Update: see a thoughtful perspective in Chris Edward's blog.

Tantalizing But Flawed

I would love to know the real scoop on the semiconductor challenges and drama involved in developing a high-end gaming console like Microsoft's Xbox 360. A surprising story originating at DAC, EETimes.com - The truth about last year's Xbox 360 recall dangles some tantalizing clues.

I find the story frustrating and a bit flawed in helping to get to the truth of the matter. The article blames Microsoft's troubles on "bypassing an ASIC vendor to go directly to TSMC". But then it mentions ATI Technologies as a likely ASIC vendor. Huh? ATI, an ASIC vendor?

I would call ATI more of a "contract design house" in this deal. They have considerable graphics IP, and designed the GPU for the Xbox 360. (NVIDIA designed the GPU for the original Xbox.) Perhaps Microsoft decided to take only the design (netlist or GDS2) from ATI, and manage the silicon operations and production ramp themselves. That could be where they went astray. By not contracting with an experienced semiconductor company (like ATI or NVIDIA) to manage all the silicon issues, they exposed themselves to more risk. And maybe that came back to bite them in the form of the product defects exemplified by the "red ring of death" and led to product recalls.

Penny wise and pound foolish, Microsoft?

DAC 2008 Meta-Must-See List

That's right, readers. This is a list about lists!

I search the internet, so you don't have to.
-- From "your friend in the EDA Blogging business". (apologies to Tom Shane)

• Cheesy John Cooley's Must See List for DAC
• Ten top technology developments to see at DAC, SCDsource (Richard Goering)
• Gabe's teaser of Gary Smith's list. Looks like you have to visit them at DAC to get the real list. Gary has enough clout that companies issue press releases when they make his list!
• Gary Smith interviewed on YouTube. He names some significant trends in EDA this year, including Analog and Low Power design. The "Software" trend is a little harder to see; I know Gary has been calling for ESL to take off for a few years now.

What "EDA Blogger Birds" Could Squawk About

Next week at the Design Automation Conference, a few leading EDA bloggers are arranging an impromptu "Birds of a Feather" session at DAC. There have been several posts discussing the event. Informal Blogging Event at DAC Gains Interest has a good summary.

Although I'm not sure I'll be going down to Anaheim, I'm very intrigued by the event and would like to attend. What topics would EDA bloggers talk about? Here are some that I would like to discuss with my brethren:

• Online magazines, vendor communities, "DeepChip", and blogs: what each is good for.
• What to write about. What not to write about. What I really want to write about, but am afraid to.
• Frequency and regularity of posting.
• How to build audience. How to track audience. Support each other through linking and commenting. Use pictures? Polls?
• How to foster discussions. Pros and cons of comments. Need for an all-EDA bulletin board.
• Team blogging. (multiple authors contributing to one blog)
• Beyond blogging: social networks (LinkedIn, Plaxo). The Twitter phenomenon.
• Can you make any money? Ads: google or sponsored.
• For readers: how to find and follow blogs.

Incidentally, I've been blogging about EDA and Semiconductors for three years! My first post was about TSMC and low-power design; topics that are if anything, more relevant today.

EDA Earnings Recap

Quarterly financial results are in for the major EDA vendors. This was Magma's turn to disappoint, causing the share price to drop almost 30%. Mentor Graphics stock has performed the best, closely followed by Synopsys. Links to results are below.

• Cadence Languishes On - Sramana Mitra on Strategy
• Magma Design fiscal 1st-qtr outlook disappoints investors.
• Synopsys Posts Financial Results for Second Quarter Fiscal Year 2008. Higher (non-GAAP) earnings.
• Mentor Graphics Reports Fiscal First Quarter Results. Quarterly loss. "Difficult environment". Cost/headcount controls. More importantly, projecting "a strong second half".

Conformal ECO Designer: Successor to ECO Compiler?

Without too much fanfare, Cadence has introduced a tool to help automate ECO creation: Cadence Encounter Conformal ECO Designer Improves Logic Designers' Productivity. At least I didn't see too much fanfare in the engineering press. However, it was mentioned in Cadence's recent earnings conference call:

... Cadence’s Encounter Conformal ECO Designer, a unique and automated capability to address the extreme pressure customers face to deliver on schedule while still achieving targets for product cost and quality. ECO stands for Engineering Change Order and unfortunately for designers these are all too common.

If you've been in the industry a few years, you'll recall that Synopsys had introduced a tool, ECO Compiler, for the same purpose. It never seemed to gain much traction, and Synopsys eventually abandoned it. I never had the chance to use ECO Compiler and I don't know why it didn't succeed. I heard some mention that it's a hard problem to solve, and that the market may have been limited. It's the type of tool that when you need it, you really need it. But you don't need to buy dozens of licenses.

It will be interesting to see how Conformal ECO Designer does -- whether it's better technology, and whether Cadence is able to make the business equation work.

From the Department of Redundancy Department

Dobbs Code Talk - Redundancy in Programming Languages discusses why sometimes redundancy is a good thing. Like in accounting, or computer programming. (Or HDL programming.)

Key conclusion:

Many programming language designers mistakenly assume that removing redundancy makes programmers more productive. ...

Well-designed redundancy can, however, dramatically improve productivity with its ability to uncover errors early in the development process. ...

The trick, of course, is figuring out which redundancies are good, and which aren't.

Countdown to DAC: Design Automation Conference

If you're involved in the EDA or ASIC industries, you should consider going to 45th DAC Home: Design Automation Conference.

There are early registration discounts available for signing up before May 19, so get moving!

I mostly like DAC for the exhibits and the panels. A lot of the papers go over my head -- often PhDs presenting their thesis research on "new routing algorithms that did x% better on university benchmarks."

Profile-Guided Optimizations for Software Development

Not being a commercial software developer, I hadn't heard of Profile-Guided Optimizations (from the blog of the Opera Browser Desktop Team), but it sounds clever: run some "real-world benchmarks" through your application, and then recompile the application to optimize for the code path followed most often.

Is this common in software engineering? Do EDA tools do tricks like this for best performance? Let's hope so.

Weirdest EDA Acquisition Ever?

Just read about Synopsys Invests In Prover Technology and I decided to post it without further research, just to react to the article.

From reading the press release, I'm really left scratching my head. Is this for real? It's not April 1, right? I am very curious to see how much synergy exists between "railway signal design automation" and EDA!

A missing link in tech history

For those interested in the history of our industry -- and who of us shouldn't be? -- here's a news item of the pre-electronic (even pre-electrical) origins of computing:

A missing link in tech history - San Jose Mercury News tells the story of the construction of the "Babbage Difference Engine", which was designed but never built by 19th century inventor Charles Babbage. This is truly an engineering marvel. Frankly, I'm amazed that it works! Here's a video showing some details of this mechanical masterpiece in operation. I certainly want to head over to Computer History Museum in Mountain View to check it out.

While we're on the subject of history, here are other good resources to check out:

• Intel Museum (online and in Santa Clara)
• The Chip History Center (online)
• IEEE Virtual Museum (online)

Blessed Perl

I just spent three days in great Advanced Perl Programming class taught by the Anderson Software Group. This was the best class I've taken in a long time. One of the most satisfying things to do at work is to develop a well-crafted program (usually in Perl) and see it working smoothly to automate my own or someone else's work. The class exposed me to things I'd always wanted to know about Perl, including Object-Oriented Perl, GUI building, and interfacing to databases, networks and C programs. Great stuff!

We worked from Anderson's class notes, but the reference text for the course is Advanced Perl Programming from O'Reilly. See my other favorite programming books on the CAD Engineer's Bookshelf.

I'm hearing rumblings that Python is a "better Perl", designed from scratch for object-oriented programming. I guess it lacks that Perl syntax that can make a program look like hieroglyphics? This sounds like the next language to learn.

Apple buys a CPU company

Wow, I didn't see this coming: Apple disses Intel's Atom, buys PowerPC designer P.A. Semi. Very interesting. I had been vaguely aware of P.A. Semi, but didn't know where they'd find big demand for their advanced PowerPC CPU. And Apple has become more of a system designer than a chip designer. So I wouldn't have guessed that they'd buy a Semiconductor IP company. Some have twittered, "why not AMD?" For that matter, why not Transmeta, if they're looking for a very low power mobile CPU?

Congratulations, P.A. Semi! It will be fun to see how this plays out.

Forbes article

Update: color analysis from Chris Edwards.

Stop Me Before I Schwag Again

Just got back from the TSMC Technology Symposium. I'll think about what I can share from that always-valuable event. But what I have on my mind, in the wake of Earth Day, is the schwag that us engineers accumulate, and how we just can't stop it!

• Another conference, another tote bag. My closet is overflowing! And, another non-recyclable badge lanyard that will have to be thrown out. I wish that conference organizers would "think green" and give out less "junk", and distribute reusable or recyclable merchandise. Of course, I need to look in the mirror as well. Why can't I say "No" to this stuff? I'm making some progress in turning down trinkets, but it requires eternal vigilance.
• Will engineers do anything for a T-shirt? Although I love them, my home is overflowing with shirts from vendors and from runs and rides that I go on. I've become more discriminating: a vendor's white t-shirt won't make the grade, nor will colored ones with a non-clever design. What I am amazed by is how easily I can give these shirts away to other engineers. I put a vendor's black t-shirt out in the break room with a "Free Shirt!" Post-It note. Within five minutes, it disappeared! I have successfully followed the mantra Reduce, Reuse, Recycle. In the words of Fake Steve Jobs, namaste.

DFM heads into the foundry

And we're back to the "Hacking Cough" blog for this analysis of DFM heads into the foundry. The post explains an innovative announcement from TSMC whereby they will offer as a service Blaze DFM's power & variation optimization capability. The innovative part is that instead of a chip design company buying the EDA tool, you pay for it as a service from your foundry (exclusively TSMC at this time).

One thing I'd wonder about is how design teams can accurately convey their timing environment to TSMC (across all modes and corners) such that these optimizations don't break timing. Running sign-off STA is not quite as simple as "just send an SDC file over". :-)

Good Blog, Odd Name: Hacking Cough

I've found a semiconductor blog to recommend, with the curious name of Hacking Cough. It's better than the name implies! One more salvo in the 32nm war is a nice overview of where IBM, Intel, TSMC, and others are headed with their 32nm process technology recipes, and their different approaches to solving scaling and power consumption problems.

NVIDIA Powers Hardware-Accelerated SPICE Simulator

The multi-core future of EDA is just starting to appear. NVIDIA Powers Hardware-Accelerated SPICE Simulator is an exciting announcement of a real EDA application (Fast SPICE) running on massively parallel GPU hardware. Will general purpose GPU (GPGPU) computing become the acceleration platform for EDA?

SNUG SJ 2008 Report

For my report on this year's SNUG San Jose conference, I'll point out the major themes that cropped up across multiple sessions. If you're a Synopsys customer, you can see all the papers and presentations at the SNUG web site.

Low Power Everywhere

Low Power support is becoming pervasive in design flows. Both in design and verification, tools are supporting techniques such as Clock Gating, Multi-Vt, Power Gating, State Retention, Multi-Voltage, and Dynamic Frequency and Voltage Scaling.

Of course, for an EDA company, this requires a new name to designate these new features. So, Synopsys is calling it their "Eclypse" flow. (Note the funky spelling to give fits to spell checkers everywhere.) I don't think this name matters much to ASIC engineers -- do you care what the "Galaxy" or "Discovery" platforms consist of?

DC Topographical Uber Alles

DC Topographical, which is Design Compiler's inclusion of "virtual layout" during synthesis, is becoming mainstream. The newest edition is DC-Graphical. It adds congestion reporting and optimization, and a GUI to help visualize and debug virtual layout-related issues. It certainly makes more sense than using traditional wireload models, though you could run into correlation issues if the virtual layout floorplan is very different from actual.

Blues Compiler Rocks

The biggest treat of SNUG was the first public west coast performance of Blues Compiler, Synopsys' house band. To be honest, I hung around to hear them play out of curiosity. I figured it would be a bunch of guys who used to play in college and still liked to goof around with their instruments. Boy, was I in for a pleasant surprise! Featuring CEO Aart on electric guitar, and "Diva" Joanne W on vocals, this band absolutely rocked! They sounded very professional and played a number of sweet electric blues/rock songs. I'd compare their sound to Janis Joplin's, who I am a big fan of. Absolutely recommended to check out if you get a chance. They usually play at Boston SNUG, and I hope they'll be back in San Jose in the future.

A review of the performance would not be complete without a nod to the "Solid Gold" Marcom Dancers, who succeeded in getting a bunch of engineers in a banquet room dancing to the tunes. Quite an accomplishment. I was impressed and hope to get dancing lessons from "Crazy Legs" Shankar H in the future.