Development work is five times cheaper here

‘Development work is five times cheaper here’ is the claim by the CEO of ATI Technologies, commenting on their Hyderabad R&D center.

There are certainly very attractive aspects to setting up shop in India, but this article is a little over the top. I wonder if it's because this story is published for an Indian audience, or if it's because ATI has only been doing R&D there for a year, and perhaps hasn't seen the tradeoffs through a full product cycle?

The Power of the Xbox 360 GPU

The Power of the Xbox 360 GPU is a very informative interview with a VP of Engineering at ATI. He speaks in reasonable detail about what's in the custom graphics chip of the Xbox 360 game console. He contrasts it with conventional GPU architecture, and of course espouses why it must be better than what NVIDIA will provide in the Sony PlayStation 3 GPU.

The Xbox 360 GPU, "Xenos", is actually a two-chip implementation, and one of the chips has a big embedded DRAM! Although lots of ASIC vendors talk about doing this, you don't see it often in practice. Performance-wise, it makes sense, as you get huge memory bandwidth via the very wide interface to the DRAM.

SNUG: Synopsys Users Group - San Jose Conference at a Glance

SNUG is coming! The flagship San Jose Synopsys Users' Group meeting starts on March 20, 2006. Here is the conference schedule.

I've always felt this is the best conference for the "in the trenches" chip design engineer. It's very practical, with good tutorials, keynotes, and a healthy dose of user papers.

As I was signing up this year, I noticed that almost all the sessions I signed up for were Panels or Tutorials, not User Sessions. I wonder if the conference schedule is shifted away from user papers this year, or if my interests just happen to be with the other topics. It would be interesting to look at the split of types of sessions over the years. Well, not so interesting that I'm actually going to do the study, though. ;-)

Library standardization effort takes flight

Library standardization effort takes flight

There is a need for standardization of modeling for Statistical STA, though that whole technology is not well understood. It may be too early to standardize!

It would be great to settle the CCS vs. ECSM divide, however. These are essentially the same modeling approach, yet defined differently by Synopsys vs. Cadence/Magma, respectively.

I have sympathies for Si2 in trying to forge these standards across EDA companies. I was more involved in the days of Liberty, DCL/DCM, and ALF standardization, and it was very hard to get cooperation across all EDA vendors. They see Standards as an area to maneuver for competitive advantage.

Leakage takes priority at 65 nm

Leakage takes priority at 65 nm in EE Times is a nice survey of the experience of 65nm IC designs so far.

I noted that Statistical Timing Analysis was called a "must-have" technology, because of all the combinations of operating conditions when you have multiple voltage islands.

Two Win Prestigious Engineering Award - New York Times

Two Win Prestigious Engineering Award - New York Times

Cool! It's nice to see a couple of great engineers prominently recognized for their great contribution to technology (37 years after the invention of the CCD)!

Down with FinFETs, Up with Materials!

EETimes.com - FinFETs may never come in, IBM fellow claims

FinFETs (transistors where the channel gets pinched off from both sides) sound like pretty slick design solutions, and several companies and many universities are studying them. But this IBM researcher predicts that they aren't manufacturable. Instead, industry needs to focus on advanced materials for the traditional "planar" transistor technology.

Managing variations in IC physical design

EETimes.com - Managing variations in IC physical design is a great paper on the design closure challenges facing nanometer-scale IC design.

The author, Shankar Krishnamoorthy of Sierra Design Automation, describes the very typical timing analysis and design closure flow, where many different modes and PVT corners must be considered, yet closure tools only understand one or two of the scenarios.

The rigorous treatment of design variation, classified in a matrix of variablility "causes" vs. "effects", is the best treatment I've seen in a public article. (EDA vendors will show similar analyses when privately pitching their new variation-aware products.)

Surprisingly, the author does not conclude that "statistical" timing analysis, which is all the rage in the EDA community, is a panacea. He points out the difficulties of getting statistical characterization data for process, libraries, and interconnect. He also asserts that Hold time violations require analysis at whichever corner most aggravates a particular violation (calling for multi-corner analysis).

Very thought provoking! It will be interesting to see what products Sierra comes up with to address this growing IC design closure problem.

Teardowns find 'Microsoft Inside' Xbox 360

Here's another, more detailed, Xbox 360 "reverse engineering" article: EETimes.com - Teardowns find 'Microsoft Inside' Xbox 360.

Most of the chips have Microsoft's label on the package. At least in the case of the GPU, I believe that Microsoft bought the design from ATI and is paying royalties. I've read that this is a different business model from that of the original Xbox. Microsoft apparently wants more control over the silicon and any cost reduction efforts.

Microsoft's Red-Ink Game (Xbox 360)

Microsoft's Red-Ink Game provides cost estimates of the just-released and super-hyped Xbox 360 game console. Estimates are that it costs $126 more that the sale price to build the box.

Looking just at the chips, this machine has some expensive silicon:

Semiconductors alone account for $340, -- more than 72% of the materials cost -- iSuppli estimates. One key component, the IBM-designed microprocessor chip at the center of the console (see BW Online, 10/25/05, "Inside IBM's Xbox Chip") costs about $106. Both IBM and Chartered Semiconductor (CHRT) of Singapore are building the chip for Microsoft.

ROOM FOR IMPROVEMENT. Analyst Chris Crotty with iSuppli says that as both companies improve their manufacturing efficiency and production yields, they will likely reduce the chip's cost by 20% to 25%. The same will likely apply to ATI (ATYT), which is building the graphics-processing unit, or GPU, for the Xbox. iSuppli estimates that the chip is the most expensive component in the system at $141.

And how about the cost of the Sony PlayStation 3, to be released next year?

Crotty expects that Sony's loss on the Playstation 3 may be even wider, as the cell processor that IBM, Toshiba, and Sony designed for the system is more complex.

Estimates vary as to how much the cell processor will cost. Richard Doherty of Envisioneering Group in Seaford, N.Y., expects the cell chip to cost about 50% more than the Microsoft chip. "Based on what we've seen so far, the Playstation 3 could cost as much as $600 to make in today's pricing," Doherty says.

And Crotty says that since it's a more complex chip, its price will fall more slowly than the price on the Xbox chip.

Ouch! No wonder the games cost $60 per title, to make up for the hardware losses.

Sramana Mitra on Strategy

I enjoy this blog by Sramana Mitra, who is a technology and business prognosticator. His Her blog both covers the big picture and contains nuggets of individual business/career opportunities, such as

Configuring and managing Home Networks will be a big profession, and this job cannot be outsourced as easily. A largely non-tech savvy consumer population will demand that service personnel come out to their homes and fix things. Who pays? Consumer or Carrier? Without this support, Convergence will not cross the chasm.

-- Sramana Mitra on Strategy; Blog Archive; Cisco: Inching Us to True Convergence

11/22 UPDATE: A loyal reader (from India) pointed out that Sramana is a woman, not a man. My apologies! I've corrected my wording.

ICCAD keynote | Gabe on EDA

Tets Maniwa's article (on the Gabe on EDA blog) summarizing the ICCAD keynote is a well-written overview of the Cell processor design tradeoffs.

I'm sorry I missed ICCAD; it's right here in Silicon Valley. I need to get on the right mailing list to hear about such things. It's not as practical a conference as SNUG, but it's a good resource for a look at future design technology.

EETimes.com - Alarming export: engineers

For a long time (since even I was a college student), US Engineering graduate schools have been populated primarily by foreign-born students, particularly from China, Taiwan, and India.

It used to be that such student would typically stay in the US to work. This was controversial, requiring H1B visa, and some allegations of taking American jobs or depressing wages.

Today, these students aren't necessarily sticking around. They're going back to work in their home countries, where they may be more comfortable or sense more opportunity. An example of this is described in EETimes.com - Alarming export: engineers.

Now these very bright students are taking their knowledge and work ethic back home. It's probably a net loss to the US to not have them sticking around. It shows you should be careful what you wish for!

Semiconductor Workforce Demands and Opportunities

Semiconductor Workforce Demands and Opportunities lists the specific job titles that semiconductor employers are looking for hardest.

It's an interesting list. Some of it makes sense, some doesn't. It would be best for me to look into the Analog/Mixed-Signal (AMS) field, since I'm not qualified to fill the African-American or Female Technicals openings.

Magma plans tools to address complexity challenges

Magma plans tools to address complexity challenges is an intriguing pre-announcement. What will this "thing" be?

There's always tension between wanting a "one-stop-shop" with a highly integrated environment and flow, and wanting "best of breed" tools that produce the best, fastest results. Best of breed usually wins. Getting to an integrated environment? That's what CAD departments are for. ;-)

John Cooley's DVcon'05 Trip Report

DVcon'05 Trip Report:
-or-
A Census of 338 Engineers on Design Verification Tool Use

is chock-full of EDA data painstakingly compiled by John Cooley.

It's nicely organized, and the summary at the top of each subject is well worth a read. As you get further into each article, there are a lot of one-line responses that aren't very informative, though you can get a feel for what other companies are doing.

Intel's Ultra Low-Power Process

There was a story a couple of days ago about Intel announcing an ultra-low power 65nm process. I've been looking around and couldn't find much technical detail, but New Intel 65 nm lithography promises reduced leakage for small devices at Tom's Hardware Guide has the most detail.

The power reduction is through a three-pronged attack:

1. Increasing treshold voltage. This is familiar to all nanometer-scale digital IC designers today.
2. Low Damage Junction Engineering. Uh, that's some real process engineering, and I don't have much insight.
3. Increased Gate Oxide Thickness. This is very interesting and counter to scaling and performance trends. But, when the gate oxide is only 3-5 atoms thick, you have to question "how thin is too thin?". The article just mentions making the oxide thicker. Presumably this is less risky than utilizing often-mentioned but not-in-production High-K Dielectrics.

Startup claims FPGA lead with asynchronous logic

EETimes.com - Startup claims FPGA lead with asynchronous logic one of a handful of claims for products based upon asynchronous logic design.

I'm very intrigued by this idea. It has the promise of removing lots of overhead in chips for clock distribution and balancing. Not only does all the synchronous clock overhead use a significant amity of chip area, but it uses up a large amount of the standard cell power consumption! Every one of those clock buffers toggles twice per period, giving it a "toggle factor" of 2X.

I don't recall asynchronous logic design being taught in any of my engineering classes. There need to be more resources to learn about it.

Another big roadblock is that there is not the EDA infrastructure for asynchronous design. All the commercial synthesis, timing, and test tools assume synchronous design.

Designing ICs with the 'X' Architecture

EETimes.com - Designing ICs with the 'X' Architecture is a great exposition of the emerging design style of using diagonal interconnect in addition to the traditional Manhattan (horizontal and vertical only) routing.

The good news about EDA

It is good to recognize the exciting things that our industry is accomplishing, as described in EETimes.com - The good news about EDA by Richard Goering.

I agree that SystemVerilog looks to be a better way to design and verify. It's more productive, removes some Verilog ambiguity, and has better support for formal verification.

I don't know the prospects for OpenAccess (hope it's not another CAD Framework Initiative or CHDSTD), but hope it succeeds. As Richard says, why should every startup (and every corporate CAD department) have to redevelop the infrastructure for EDA tools?

Don't know much about SystemC. Let's start using SystemVerilog first.