Early in my career, I got to visit the IBM Burlington fab when they were introducing a brand-spanking-new technology called "CMOS". Little did I know that would be my last chance to set foot in a semiconductor fab. So, I'm always fascinated to see how things look today. Some things I learned:
Created by several fellow EDA bloggers,
this is an intriguing new EDA/Chip Design site
worth visiting and contributing to.
I know that several bloggers and old ASIC hands wanted to put together an open community for sharing opinions and experiences, and this is the most substantive effort to date. (I tip my hat to John Ford's now-defunct "DFT Digest" site, which was a pioneer in this area.)
I couldn't resist reading an article titled
Apple's HR Department Is Obviously Filled With A Bunch Of Sadists!
Could you figure out the answer? To my frustration, I couldn't, without peeking at a few of the comments. It makes perfect sense now. Not a bad puzzle!
I've read Nick's newsletter for a long time and recommended it, his web site, and his book to many people. What I like is that much of it is more sensible and less trite than so many of the job-seeking rules of thumb that you read. I don't agree with him 100%, and some of his advice seems hard to implement, such as refusing to disclose your current salary. But, he has good reasons and it's all worthy of your consideration.
I hope you are enjoying the holiday season and wish you interesting projects and prosperity in 2011!
Past history is crystal clear and his description spot on. His assessment of current and future value-add is plausible and thought provoking. Sounds dire for many silicon-centric companies, though. Will you be a survivor? What does it say for the fortunes of the EDA industry? His answer seems to be focus on system/software, complemented by C-based hardware design.
Beyond 22nm, many things get exotic. Extreme UV (EUV) has been the next big lithography change for ages -- is it finally required for 15nm? FINFETS, Carbon Nanotubes, and Stacked Die, Oh My! We're not in Kansas any more.
,
by Rob Walker, one of the founders of LSI Logic. (I have an autographed edition!)
But this is much more focused than a merchant ASIC business. FPGA itself is more like a Standard Product, with high volumes and lots of benefit from using advanced processes. Altera and Xilinx are the most leading-edge customers for the established foundries. It'll be interesting to see Intel's motives beyond just "further monetizing the fab".
It's exciting to see GPU Computing gaining traction and accolades for certain highly parallel applications. I'm anxiously looking forward to GPU Computing helping to solve EDA problems. So far, there's been some nibbling around the edges and algorithms experimented with, but I'm not aware of production EDA products based on GPU. Yet. What EDA applications would most benefit from massively parallel processing, such as is offered by a GPU?
Software is on sale in China!
So says
Software Companies Lower Prices to Fight Piracy in China, which reports that Microsoft and Autodesk are slashing prices of their OS and CAD software, respectively, in an effort to capture some revenue for their otherwise widely-pirated software.
Does the same thing happen with EDA software? The state of the EDA business in Asia is something I only know from the occasional rumor. How widespread is EDA piracy? How common is it to "crack" FlexLM? And, is EDA software already heavily discounted in Asian markets?
The last point most concerns American workers. Not only are American competing from a higher wage/cost-of-living, but what if the essential tools of our trade are cheaper overseas, as well? Strike two!
Though I'm not sure I'd always like to be his employee, it is pleasing to be his customer. Customers willing to pay a stiff premium are the sincerest form of flattery.
As my readers know, I find SNUG to be the most valuable conference for hands-on IC design engineers. I always leave with a list of new ideas to try back at work.
Why not launch your publishing career and boost your reputation by showing the cool stuff you've worked on?
Top themes:
Product-wise, Aart emphasized their custom design competitor to Virtuoso, which I don't find super exciting. It's always nice to have a more modern implementation of a workhorse tool, but not earth shattering. Synopsys bread and butter tools, which pay the paychecks, didn't get much air time.
I think some of the market share claims could be misinterpreted (90% of 32 nanometer chips), but that's standard fare for the ways vendors advertise this.
Prof. Horowitz's solution is provocative and plausible, though not a "slam dunk". I'd like him to quantify how much his approach would reduce the total cost of nanometer semiconductor design. Also, how applicable is it to domains beyond processors? Isn't it very difficult to create an "architecture generator" for each domain? For another perspective, here's a blog post reviewing the talk.
Companies on the list relevant to EDA/ASIC engineers:
SURPRISE: EDA cost per transistor is coming down the same learning curve as all the other input costs like materials, chemicals, labor, etc. (above) and it has been doing so throughout semiconductor history.
What is Wally Rhines' prescription for increased EDA value-add (and profits)? EDA vendors
... must incorporate the embedded software development and system analysis costs into their design tools and flows. To the extent this is accomplished, there isn’t a cost problem and the 30%+ per year per transistor cost reduction can be achieved. That’s why EDA companies first became involved in embedded software in the mid 1990’s. That involvement will grow as EDA companies take on more responsibility for the total design challenge and its costs. It’s just part of the evolution of roles in the semiconductor industry. (Walden C. Rhines is chairman & CEO, Mentor Graphics Corporation.)
Although in the short term there are still plenty of us fighting it out for nanometer-scale timing (and now power) closure, the focus on software and systems is plausible for the long term. We must find quantum leaps in productivity to take advantage of Moore's law in semiconductors.
You can see other trip reports and interesting links in the delicious.com sidebar of my blog, where I post EDA and Semiconductor links.
