DAC Meta-Blogging

If you're at DAC and haven't yet overdosed on "Social Media", please stop by Tweet, Blog or News: How Do I Stay Current? this afternoon. I'll be on the panel, sharing ideas for how to wade into this trend in the most efficient way. Listen, ask questions, and say Hi.

Denali Software is a great supporter of DAC. They teamed up with Atrenta and Springsoft to start the I Love DAC program and provide dozens of complimentary Exhibits passes for the conference. They also ran good-natured competitions for EDA's Next Top Blogger and EDA's Community Superheroes. Congratulations to Karen Bartleson of Synopsys for winning the Top Blogger distinction, and Joy Matsumoto from Cadence for her great efforts to support charitable causes.

The Road Less Traveled

DAC begins its second full day in San Francisco, and I encourage you to take advantage of the opportunity. I was up there yesterday and found a great variety of vendors, panels, and other events to check out. In the morning, crowds were pretty sparse, but there was a definite pick-up in the afternoon. In particular, there was a lot of congestion around the prominent Synopsys booth, next to a well-visited Standards area.

Fellow blogger JL Gray in front of Twitter Tower (image courtesy jlgray)

Synopsys is diving into "Social Media" in a big way at DAC, so it's worth checking out Conversation Central with its variety of sessions on how to understand and make the best use of these new communications media. The Twitter Tower is a novel way to take in DAC's zeitgeist.

That said, I'd encourage everyone to venture out beyond the comfort and safety of the big EDA vendors! If anything, I de-emphasize visits to the top vendors, because one can follow their announcements and arrange meetings any time of the year. But DAC is a unique opportunity to see a great variety of vendors, from the "second tier" specialist that you're not quite familiar with to the Mom & Pop startup that just rolled out their shingle for their first DAC. To make this discovery more purposeful, I flip through the Exhibitor descriptions in the DAC program and highlight the booths of companies that sound remotely interesting. That way, you can avoid wasting time by ping-ponging between North and South halls. Go for it!

On a lighter note, on Sunday I made my way to San Francisco for an EDAC reception. Before that, I explored Golden Gate Park (stunning!) and snapped a few pictures.

The first perplexed tool user.

Real-Time DAC Tweets

The next best thing to being at DAC is to watch the "tweets" posted by attendees--

Getting to DAC

There has been no end of posts about "going to DAC", what to see, what's hot, etc. But, how to actually get to the venue? Since I'll be making the trek solo from Silicon Valley and am phobic about the hassle and expense of driving and parking in SF, I'll share some public transportation research.

Caltrain

Caltrain provides service on the San Francisco Peninsula. Here's their schedule. If you catch one of the "baby bullet" express trains, it's less than an hour from San Jose to San Francisco. Fares from San Jose are

One Way	$7.75
Day Pass	$15.50

From the Caltrain station in San Francisco, you'll need to get to Moscone Center. In previous years, DAC ran a shuttle for this, but I don't see any notice of it this year. You can either walk or take the city bus. It's only a one-mile walk, so I plan to try this and count the back and forth as my exercise for the week. Google has a nice map showing both the walking route and links to bus schedules, if you prefer. View Larger Map

BART

Bay Area Rapid Transit has stations on the Peninsula and East Bay (Fremont is nearest to Silicon Valley) and can take you to Montgomery Station, only 3.5 blocks from Moscone Center. The One Way fair from Fremont to Montgomery Street is $5.60.

Synthesis Gets Interesting

As a pleasant surprise, there's quite a bit of activity and emerging excitement in the area of synthesis, just in time for this year's DAC.

Physical Synthesis

Oasys Design Systems has come out of stealth mode with rather incredible performance claims.

It's exciting to hope for a revolution in synthesis. Put me in the "show-me" camp. It's (relatively) easy to meet 80% of what Design Compiler can do, but there are many features and tricks developed by DC over the years, making it a hard tool to displace. Synopsys has certainly seen strong competition, including from Ambit BuildGates (acquired by Cadence) and most recently by Get2Chip (now Cadence RTL Compiler). What often happens is not that king DC is overthrown, but that the competition lights a fire under Synopsys and their tools will improve at a much faster pace than market dominance would dictate.

What's interesting about Oasys are the tremendous claims about capacity and run time, and the emphasis on physical synthesis, combining logic synthesis with placement and optimization. The company also has impressive board members, including Sanjiv Kaul (former implementation GM at Synopsys) and, re-appearing to EDA after a long hiatus, Joe Costello (charismatic and successful former Cadence CEO).

ESL Synthesis

For several years, EDA industry analyst Gary Smith has been calling for the ascent of ESL (Electronic System Level) design. He was already called an ESL evangelist back in 2006! It's been the next big thing for a while now. It seems to follow the industry's progression from transistors to gates to RTL, but RTL remains the mainstream design method.

In the context of design implementation, ESL implies synthesis at a more abstract level than RTL. This year, there appears to be considerably more buzz, and not just from Gary. See, for example, recent posts by John Cooley and Richard Goering.

Key players include

• Forte Cynthesizer
• Mentor/synthesis CatapultC
• Cadence C-to-Silicon
• Bluespec
• Synfora Pico Extreme

My apologies for any I've overlooked--I'm learning about this field. One point of concern is that there isn't a consensus on design language/dialect, which varies by vendor over C, C++, SystemC, and proprietary languages/extensions. That can impede adoption. It was Design Compiler that established the de facto standard for Verilog RTL synthesis subset, and this provided a common point for customers (and competitors) to converge on.

It's nice to see continued innovation in this critical area of IC design, and merits further investigation.

Looking Forward to DAC

As most everyone is aware, the big conference in the chip design software world, DAC, runs July 26-31 in San Francisco. I'm looking forward to it and plan to be up there most days. Some prognosticators have posted their "must-see" lists. (Gary Smith, John Cooley laying out the law for aspiring vendors) and there will be more to come.

Rather than calling out specific companies, I'll share some of technologies that I'll be looking to learn more about.

Low Power

This is one of the genuinely valuable and necessary "next big things" in methodology.

Datapath

I've always been surprised that specialized datapath techniques aren't more successful. It seems like you either use an advanced RTL synthesis tool, or design datapath by hand. There's not a lot of in-between.

MCMM (Multi-Corner, Multi-Mode)

It sounds like the solution to many problems. But how well does it really work -- how scalable is it?

parallelism, multi-threaded, multi-core, GPGPU

How will EDA ever catch up to designs scaling by Moore's Law? By using the parallelism available in today's CPUs and GPUs. Multi-core is working today for 4-8 cores, but may hit a wall beyond this. And what about the tremendous parallel computational power in your Graphics Processing Unit? A few EDA tools are leveraging the CUDA platform; where will it pop up next?

Update: check out Richard Goering's interview with EDA luminary Kurt Keutzer on this topic.

Asynchronous Design

This is my token research-y interest. Synchronous design is what we all learn in school, and there's a plethora of tools (namely, the EDA industry) to automate such designs. But there are drawbacks with respect to area and power. Can we learn a new way to design, and develop new sets of IP and automation tools?

You Probably Believe We've Landed on the Moon, too

Don't believe everything you read. There's an insightful behind the scenes exposé on DeepChip about a technology web site that turns out to be a marketing venue for a group of EDA start-ups. Nothing wrong with that, but the disclosure of who's behind it took some digging and questioning to tease out.

Of course, one would be naive to assume this doesn't happen elsewhere in the media. Even Mr. Cooley's beloved DeepChip, with its purported user-generated content, can be gamed. When you read a glowing endorsement of an EDA tool, ask yourself questions such as

• Who wrote this? Are they "anon"?
• Did they really write it? Or could it have been "ghost written" by the EDA vendor and submitted in the customer's name?
• What is the author's interest in the vendor? Does the author's company have a financial or other interest in the vendor's success?

Nothing beats the testimonial of someone you know and trust, other than your own hands-on evaluation.

p.s. in honor of Apollo 11's 40th anniversary, read more about Apollo Moon landing hoax conspiracy theories .

DAC Appeals to Users

When I first started attending DAC (1990 in Orlando), as an ASIC designer who'd recently joined an EDA group, I found it disorienting. The exhibits floor seemed like a circus with attendees rushing from one booth to the next to collect the best schwag (some things never change). I dutifully sat in paper presentations that sounded interesting, but I soon realized they weren't addressed to designers or users. I came to think of them as "PhD theses showing a routing algorithm that performed 13% better on an academic benchmark". Not to belittle those papers -- the mathematics and rigor impresses me greatly, but I don't understand all of it or apply it in my job.

Over the years, DAC has become more user friendly. The panels in particular are often informative and sometimes provocative. I find that I'm getting more and more out of DAC.

This year, there's an explicit "User Track" at the conference. I'd like to share a description of the User Track while presenting the first guest post on John's Semi-Blog. Please enjoy!

User Track at DAC:  Learn from Your Peers

Soha Hassoun
Tufts University
46th DAC Design Community Chair

Leon Stok
IBM
46th DAC New Initiatives Chair

Today’s connected world makes it possible for you to work from everywhere.  Yet, there’s only one place where you can learn how your peers successfully applied design tools to chip design and where you can exchange valuable experiences:  the new User Track at this year’s DAC.

The three-day User Track features 40 presentations that run in parallel with regular technical sessions.  Speakers include expert designers from Cisco, ClueLogic, Fujitsu, IBM, Infineon, Intel, Qualcomm, Samsung, STMicroelectronics, Sun, Texas Instruments, Virtutech, Xilinx and others.

Identifying Front-End Challenges

Power planning and verification continues to be hot.  A team from NEC will detail an automated flow to pre-characterize the power consumption of a set of basic components starting from their behavioral description in C, down to their power estimation at the gate-level netlist.  A team from Cisco will describe the use of a power noise analysis tool to analyze system power integrity.  Engineers from Texas Instruments will illustrate how they used an EDA tool to integrate complex multi-power/voltage domain design.  Intel engineers will present a flexible, high-level power management modeling and simulation framework for power architects.  And, a team from STMicroelectronics and ST-Ericsson will outline an exploratory and refinement-based power planning system.  Also, Intel engineers from India and Israel will offer a novel direction for using abstract executable models to verify power management protocols.

Tackling Backend Challenges:

In the Practical Physical Design session, a team from Intel will discuss how they tackle ECOs as late logic changes delay the process and register arrays occupy more than half of all transistors of modern designs.  Qualcomm designers will describe how they build their semi-custom methodology and STMicroelectronics engineers will outline e how they use the IP-XACT standard from Spirit to enable IP reuse.

Accurate power supply and substrate noise analysis remains a challenge, and practitioners from Qualcomm, IBM, Samsung and Kobe University will show how they attack the problem.  Texas Instrument designers will show how to analyze blocks for reuse in multiple metal stacks.  Intel engineers will highlight their approach to assessing design feasibility early in the process to avoid problems later.

A team from Stanford University, Rambus and Netlogic describes a way to tackle analog reuse as it becomes as important as reuse is in digital design.  A group from Cadence and several Taiwanese universities will describe their approach to integrate MEMs in mixed-signal designs.  Engineers from NXP and Magwel tackled the problem of analyzing substrate noise and will present their results in 90nm process technology.  With complex circuits often needing an integrated approach to physical and electrical verification, a team from SysDsoft and Mentor describes how they accomplished this on their designs.

In addition, join us for an Ice Cream Social Wednesday from 1:30pm-3pm where 42 posters will offer an opportunity for you to mingle with other EDA tool users. 

Access to the User Track is included with the full-conference registration.  Or, register separately for the User Track and get access to the keynotes, in addition to the User Track.  For more details, visit:  www.dac.com.  We look forward to seeing you in San Francisco.

###

For more information:

Nanette Collins

Publicity Chair, 46th DAC

(617) 437-1822

nanette@nvc.com

The Year DAC Changed Forever

There is so much good DAC material coming out; EDA is hitting critical mass in the blogosphere. There's a new social network site "I Love DAC" that ramping up, where I was delighted to see this flashback from the heydey of EDA: 1991: The Year DAC Changed Forever - The DAC Fan Club. (props to Steve Leibson)

Not only is the video entertaining, but it's a bona fide piece of EDA history. It's also worthwhile to reflect on the promise of Frameworks, still unfulfilled in EDA: seamlessly integrated multi-vendor tool flows. Well, at least it's job security for CAD engineers.

Denali DAC Festivities

The EDA company Denali is famous for their DAC parties. They are also running fun contests where the public can vote for the top EDA blogger or community superhero. See some new faces and vote for your favorites at

• EDA’s Next Top Blogger
• Community Superhero

And, at the party itself, watch the show and vote for EDA Idols!

DAC Attendance Deals

According to John Cooley's DeepChip site, Atrenta, Denali and Springsoft will be sponsoring 600 free DAC Exhibit Hall passes this year.

John also posted that the very popular "Free Monday" deal is coming back as well. Here's what his email described:

From: Bob Gardner [bobg=user domain=edac.org]

Hi, John,

Please inform your readers that EDAC has decided to sponsor the return of "Free Monday" to DAC this year. If they want to take advantage of this "Free Monday" registration, your readers must go to:

http://www.deepchip.com/FreeMonday.html

and complete all four pages of the registration. On the THIRD page they'll find a newly added "Free Monday Exhibits" option -- they MUST check this box to get this special registration.

On the forth page they should see a web receipt with their unique bar code confirmation on it. They must print this entire page.

To enter the DAC Exhibit Hall on Monday, July 27th, the engineer must present a paper copy of his/her entire bar code page to the Advance Registration desk located in the North Lobby of Moscone Center.

See you at DAC, John!

- Bob Gardner EDAC San Jose, CA

As for me, I've already paid my $50 for the all-DAC exhibits pass. See you there. The buzz for DAC is heating up, so watch for more blog posts before the conference.

DAC on Sale

Just a quick reminder: DAC 46th Registration Rates go up after June 29, so register today to get the early discount. See you in San Francisco!

Sean Interviews Rajeev

Though he's not as colorful as Gerry Hsu, Rajeev Madhavan, CEO of Magma Design Automation, is one of the most interesting and outspoken executives in the EDA industry. Check out Sean Murphy's Interview with Rajeev.

Rajeev founded several significant EDA companies, was apparently out-manuvered in the board room at times, and is forthcoming with what he's learned about the EDA industry and building companies.

EDP 2009 & the Return of ASIC

Electronic Design Process 2009 Symposium Program has links to the presentations from this April workshop in Monterey. I've never gone before, but it looks relevant and interesting.

I glanced at a few presentations and was most surprised to see predictions of the resurgence of ASIC vendors (vs. today's popular "COT" model). I'm not sure I agree, but it makes a certain amount of sense. It takes a lot of tools, people, and expertise to implement 45 nanometer chips. The proposition is that if it is possible to cleanly hand off at RTL, then the chip designer can focus on functionality, and let an implementation house focus on the tricks and traps of nanometer-scale design closure. But that's a big if, to be confident that the hand-off is of a properly constrained and realizable design!

Rumors of Usenet's Death Not Exaggerated

Today, I received notice from my Internet Service Provider, att.net, that they will no longer provide access to the Usenet service. This development saddens me and brings back memories of how incredibly useful Usenet was in the early days of the Internet (even pre-Web).

You could find kindred spirits of any interest available for text-based correspondence and enlightenment. I solved countless software problem (including both Windows and Linux) by searching through these groups. Who could forget groups like

• comp.cad
• comp.cad.cadence
• comp.cad.synthesis
• comp.lang.verilog
• comp.lang.vhdl
• comp.lsi.cad
• sci.engr.semiconductors

Oh, and the flame wars! (I remember there was a character outraged over the Ottoman Empire who sought to cancel every post containing "turkey", which swept up Thanksgiving recipes, as well.)

The beginning of the end was when Web access took off, epitomized by "AOL newbies" pouring onto Usenet without regard to the collegial etiquette that previously existed. After AOL, there was overwhelming growth of users, which strained the scalability of worldwide discussion forums. Finally, the death knell: Spam. When I peek at Usenet groups today, they're full of the most crude and amateurish spam. It appears that posts are not run through filters as is all of our email, and this makes the noise/signal ratio unbearable.

R.I.P., Usenet. You were one of the forefathers of what we enjoy today through the Web, forums, IM, and social networking.

Anticipating DAC

The Design Automation Conference is coming up at the end of July in San Francisco. Expect the Silicon Valley crowd to be out in force.

There's been some griping that there's no "Free Monday" this year. Instead, there's an all-days Exhibits Pass available for $50. To me, that seems like a very reasonable proposition. It remains to be seen if this will cause a significant drop in attendance, and if those who won't pay $50 are the ones EDA vendors need to see at their booths.

As the conference approaches, there will be a number of "must-see" lists, and I hope to compile my own. Right now, I don't have a very clear idea about companies to see. I do have some ideas about what may be hot, from my ASIC design implementation-centric point of view.

What Should Be Hot

• Multi-threaded & Multi-core software. Initially, these trails were blazed by startups such as Extreme DA and Sierra Design Automation (now part of Mentor Graphics). Now, all the major EDA vendors are working hard at either developing new products or retrofitting established ones. Richard Goering has had a number of interesting technical posts about how it's going at Cadence.
• Multi-Corner Multi-Mode (MCMM) analysis and optimization. This has also been talked about for a long time. It's always seemed like a good idea, but is becoming more critical at the most advanced processes and design sizes. A key question is how practical this is. What is the performance penalty to go to MCMM? Helping to solve this will be multi-threaded & multi-core software.
• Low Power. Of all the "next big thing" areas of EDA, this has struck me as the most real. There are several viable verification products based on simulation or static analysis. For implementation, there's combinational and sequential clock gating, multi-Vth optimization, and support for voltage and power domain design driven by UPF (or in Cadence's case, CPF ;-)

Ready for Prime-Time?

• I've been doing a lot of reading about variation, and various techniques to account for this. It's a fascinating new way to think about semiconductor performance. But, there is so much that needs to fall into place for statistical techniques to be used in production: tools, libraries, and a new way of thinking about design analysis.

Count Me Skeptical

• ESL. Maybe it's the market I'm involved in, where "QoR", especially performance, trump potential productivity gains at higher-abstraction design levels. This may be more attractive when time to market is everything and the QoR tradeoff not so great.
• RTL analysis & design planning. Again, maybe it's because of where I sit, but you can argue about getting too carried away with analysis at RTL. RTL is the functional description of the design. Implementation can be done "downstream" of that.

So there's a stake in the ground. I'd love to hear your comments on what the hot trends and companies will be in EDA this year. Hope to see you at DAC!

Find Your Parachute's Color on a Library Vacation

I've recommended Nick Corcodilos' Ask the Headhunter web site before for its unorthodox, yet sensible, advice to finding the best job for you. I'd recommend that you sign up for his newsletter on the web site if you like what you see. This week, he describes taking a Library Vacation(tm) for someone contemplating a career (not just job) change. It's an exciting idea!

I've seen a few friends leaving the high-tech industry, and their transition plans sometimes could use more rigor. It seems like everyone wants to get into a "green" or "alternative energy" job! I'm sure that will be big eventually, but it's better to expand your search space, and carefully consider what you would be passionate doing.

Reading Larry's Tea Leaves

Ellison Insists Sun's Sparc Still Has a Future covers statements by Oracle's Larry Ellison stating the acquiring company's belief in proprietary hardware. However, in "reading between the lines", the author suggests that Oracle might seek a big partner to drive the hardware business over the long haul.

This Week in EDA M&A

Rumors are abounding and some EDA share prices are on fire!

• Mentor will buy LogicVision, which adds complementary technology to further strengthen their DFT portfolio.
• And, Synopsys will add to their Analog IP offering by buying MIP's Analog business.

While we anxiously await "other shoes to drop", Chris Edwards provides strategic commentary on The week of the sensible deals.

Coordinated EDA

Does the EDA industry have a roadmap? is a worthy read in its entirety, but I particularly liked

The crises are piling up — software and concurrency, analog/RF, die-package-board and die stacking — and with a fixed number of EDA R&D engineers, we need to stop working on some issues. In the big picture, who wins a power format or current-source model or process variation model war is less critical to semiconductor industry health than consensus, interoperability, and moving on to fundamental design technology challenges.

This is very consistent with the efforts of companies like TSMC to get the EDA industry working cooperatively to solve more problems and add more value, by reducing overlapping development.