Bloggers Flock to ICCAD

Fellow blogger Sean Murphy has organized an EDA Bloggers' Birds of a Feather meeting at the ICCAD conference in San Jose. The conference is going on right now, and the BOF meeting is Wednesday, November 12, 4-6pm.

Whether you write or read blogs or are just interested in EDA, please come join us! It's free, and in this economy, who can pass that up? I'll be one of about eight speakers giving a short talk before the open discussion. I plan to comment on my blogging experience, give tips on finding & following blogs, and share ideas for how to get involved. Hope to see you there.

Nice Work If You Can Get It

Chris Edwards' blog post The $8m goodbye describes last-minute employment contract sweeteners given the departing Cadence executive team, including the CEO: totalling that lot up, it will cost Cadence in the region of $8m cash to say goodbye to the bulk of its former senior executive team.

Can you say Golden Parachute? I guess as long as any laid-off rank & file workers will be offered similar terms, this is fine. That'll be happening, right?

View the full CDNS chart at Wikinvest

Waiting for the Other Shoe to Drop

Cadence was supposed to announce quarterly financial results this afternoon, but they've found some "revenue recognition" questions resulting in a postponement: Cadence Announces Accounting Review and Postpones Release of Third Quarter 2008 Financial Results and Webcast

More ominously, there is wide speculation about job cuts coming to Cadence. Actually, the only "speculation" seems to be how bad it will be, whether 10-15% or as much as 25%. Scenarios are describe in Analysis: With Fister gone, Cadence layoffs may be next.

I don't know how the mood is outside of Silicon Valley or the US, but there's definitely a pallor over our industry and the economy in general. It seems like most all the EDA companies have had cuts or are planning them, and things aren't much better for their semiconductor-designing customers. At best, some companies are doing very selective hiring.

Good luck to all, and let's hope this rough spot doesn't become a quagmire.

No More Shoe Jokes for EDA

EDA pundits "won't have Mike Fister to kick around any more", as you can see by these changes afoot at Cadence.

AMD Announces Fabless Plan (finally!)

After months (years?) of speculation, AMD finally announced details of its plan to go fabless. Or is it Asset-Light? Or Asset-Smart? Let's just call it fabless, like everyone else in the industry. Read the details in A.M.D. to Split Into Two Operations - NYTimes.com. Amidst a battered overall market, AMD shares had a nice pop today:

View the full AMD chart at Wikinvest

So AMD is going to get a cash injection from a middle east "sovereign wealth" fund, plus a commitment to further invest in the fabs that they will jointly own. This is a good short-term financial shot in the arm.

We know that AMD can compete with Intel on design. The challenge has always been, how much of a disadvantage do they suffer by not having the most advanced fabs? This will be the long-term challenge, to see how well the JV will be able to compete with Intel's fab muscle as we go below 40nm and use exotic recipes such as "High-K Metal Gate". At least AMD will live to fight another day.

Update: For some skepticism on the added value and future prospects of the plan, see the story and comments under Who Benefits From A.M.D.’s Financial Engineering? - Bits Blog - NYTimes.com

Herb Reiter Tells the History of PrimeTime

In SKMurphy--Herb Reiter Interview on Fostering Static Timing Analysis Adoption, Herb Reiter talks about his career through the formative years of ASIC and EDA businesses. At Synopsys, he was instrumental in helping to define PrimeTime, and in particular in ensuring that PrimeTime was adopted and supported by the very influential ASIC vendors.

Looking back, times were simpler for EDA vendors when there were dominant ASIC vendors to define design methodology. Now, with the proliferation of fabless semiconductor design houses and the COT (customer owned tooling) hand-off model, it's harder to focus on a few key adopters, get their "sign-off certified" blessing, and reap the rewards as their customers flock to the anointed tools.

We know the result of the story--PrimeTime is the de facto standard static timing tool in the industry, and has been for over 10 years. Although in some respects PrimeTime is showing its age and could be vulnerable to competition, it is one of Synopsys' best-designed, most flexible, and robust tools.

On a personal note, I've known Herb Reiter since those MOTIVE and PrimeTime days, and he's a real professional and a gentleman. He really does seek to foster "win-win" relationships between his EDA clients and chip design companies. It's nice to see him getting publicity, and the opportunity to shed light on the development and roll-out of successful EDA products.

Top Semiconductor Infrastructure Stocks

Bullish on EDA? Check out Sramana Mitra's list of Top 9 Semiconductor Infrastructure Stocks.

I was surprised to see her put EDA companies at the top of her list, since she's described the EDA business model as "broken". It seems a combination of low share prices and the potential for industry shake-up through merger or LBO has attracted her to these companies.

HOT CHIPS Distinguished Panel Video

As an addendum to my report on the HOT CHIPS conference, I'm posting this link to the video highlights of the distinguished panel. [courtesy of IEEE Spectrum]

It was a thrill to see these giants of computer architecture talking informally and good-naturedly about the greatest hits and misses in microprocessor design. There were several references to the nearly perfect inverse relationship between architectural elegance and market success. That's right, they talked about the x86 architecture quite a bit.

Today in Semiconductor History

Chris Edwards' blog post the chip industry's quiet celebration salutes the innovations of our forebears and notes the "creative destruction" that's always been part of our industry.

Big Brother is Watching, and It's Fun

I'm at CDNLive (Cadence Users' Group), and consistent with Cadence adoption of new technology to support users, the conference features new intelligent name badges from nTAG Interactive.

"Name badge" is too mild a description for it. Each attendee gets a device the size of a large remote control with a lanyard. Besides having a traditional name tag sticker, the device functions like a dedicated PDA for the conference. It's chock full of features:

• Display of your personal conference itinerary. You know which session to go to at what time, and the paper abstract and speaker info is displayed on your nTAG screen.
• Updated conference schedule. Did presenters cancel or were new ones added? nTAG displays the current agenda.
• Social Networking! This is a fun feature. You hold up your device in front of another attendee's, and the screen displays something that you have in common (same business market, same hobbies or musical interests). And, at the push of a button, you can exchange business card information. After the conference, I'll be sent a report of all the people I met and a pointer to each session I attended.
• Online survey submission. After each session, we can rate it with a few clicks on the device. No paper required.
• A "points" system to encourage networking, filling out surveys, and attending the vendor expo. It's natural to see if you can earn more points. In this conference's case, earning enough points can get you a seat at tonight's poker tournament.

Overall, this gadget is pretty popular with attendees. We're all engineers, so we picked it up quickly and are happy to push all the buttons and explore the features.

What's sneaky is that I'm sure all this data is being transferred back to Cadence for some big-time data mining. They'll certainly track which sessions were attended and get the survey results. What else will they look at? Who networked with whom? I just hope they aren't tracking bathroom breaks. If my device lights up where I expect privacy, it's going down!

What's Hot at HOT CHIPS

I attended HOT CHIPS 20 on August 24-26 at Stanford University. HOT CHIPS' emphasis is more on computer server/system architecture than chip implementation. It's a nice small conference.

What follows are highlights of my conference notes. For more information, try to get a hold of the presentation copies, or attend next year's conference!

• x86 ISA is dominant for general purpose computing. (Interestingly, the x86 ISA was designed in a rush at Intel in a few weeks, to plug a product gap that they had. Not an elegant design intended to last for 30 years!)
• Multi-core is here today and used everywhere. (see Day of the Multicores) The jury is still out on how efficiently it can be used by software.
• Low Power design techniques are everywhere.
  • CPU architectures are changing for low power. Less speculative execution because abandoned computations waste power.
  • Clock gating is common at multiple levels
  • Dynamic Voltage and Frequency Scaling (DVFS) is used in many chips.

Press Coverage

• Ron Wilson of EDN's blog has several in-depth posts about topics from the conference
• EETimes.com articles on NVIDIA/Intel, China's Godson, and Photovoltaics.

Cadence Reaches Out

Much has been written in recent weeks about Cadence's surprise bid for Mentor Graphics and subsequent abandonment of the deal. It's not the proudest time in the EDA industry. Happening in the meantime, garnering less publicity, are two promising initiatives that Cadence is taking to reach out to customers.

• CDNLive! Silicon Valley 2008 is the Cadence Users' annual conference in San Jose, a la Synopsys SNUG. It's worth checking out if you're a Cadence user. I haven't gone regularly but plan to attend this year. I hope to see you there.
• Cadence Community is a newly designed web community with blogs, white papers, etc. It looks much better than their prior site, and I'm hopeful that it will attract a critical mass of knowledgable users. The previous site tended to have too many off-the-wall or newbie questions to have a useful signal/noise ratio.

Cadence withdraws proposal to buy Mentor Graphics

Breaking news: Cadence withdraws proposal to buy Mentor Graphics - San Jose Mercury News.

Is this related to Cadence could find it tough to raise debt for bid? (Thanks to Daniel Payne for sharing the link through Plaxo.)

An Investor's View of Top Semiconductor Stocks

Sramana has a concise summary of her take on big semi companies and their prospects at Top 10 Semiconductor Stocks - Sramana Mitra on Strategy.

Agree or not, she has a pretty good handle on technology and business and presents her case clearly. It's a good starting point to form your opinions.

Dilbert on Management

It's tempting to comment, but I'll let Dilbert speak for itself. I apologize if the formatting is messed up in the blog. Click on the strip to see it at Dilbert's site.

Merger Musings

"EDA Peggy" Aycinena has written a thought-provoking analysis & commentary (dare I say synopsis?) of Cadence's bid for Mentor Graphics in EDACafe Weekly : The Summer of Our Discontent: War Games in EDA.

She's rather cynical on the motivations of some corporate management. I think there's a good dose of truth here. How many mergers are done to appear to be "doing something", even though there's a good chance it won't ultimately create value.

But inquiring minds want to know, will some CEO be able to buy oodles of Ferragamos with the bonus from the merger?

Interview Do's and Dont's

So I'm recruiting for a design methodology engineer and have been screening resumes and doing interviews. This experience leads me to want to share some advice that not everyone seems to know.

Do

• Send your resume in PDF (Acrobat). I know that .doc (Word) is the de facto standard, but I've seen some really strangely rendered resumes coming across in Word. In PDF, it really is what you see is what you get.
• Check spelling and grammar carefully. I mean, duh! For a document this important, isn't it worth the extra effort? You should also have another person (preferably an English major :-) proofread it.
• Keep it concise. As you go describe long-ago experience, you don't need to detail everything you've done. The classic guidance is to fit your resume on one page. I know that's difficult, but once it gets to three pages or more, you're probably including too much.
• In an interview, pay attention to your "talk/listen ratio". I just made that term up. It's important to make sure you understand the question and get periodic feedback that you're on the right track before launching into a soliliquy about all that you know.

Don't

• Assume the (first) interview will be non-technical. Some companies interview easier than others. But for the case where you really get grilled, you better have done your homework. Better safe than sorry.
• List project specs or customer names (non-public information) on your resume. I'm pretty sure this is technically in violation of some employment agreement or NDA. I'm surprised at how specific some resumes are, listing the customer name, content and specs of chips they've worked on. You can "sanitize" this information and still convey the complexity of what you've done.
• Make incredible claims for your contributions. I understand that you want to put your best face forward, and maybe even puff up things a big. But when I read that you "architected, developed, and implemented" a major feature of a tool in eight months, ...

10 Great Tech Books

There's more to life than books, you know, but not much more.

Morrissey, The Smiths

I love books and "top 10" or "must read" lists, so IEEE Spectrum: 10 Great Tech Books is irresistable.

Which are your favorites?
Which ones were missed?

I've only read two of them: The Design of Everyday Things and The Soul Of A New Machine. The latter one in particular I found enthralling and ample motivation for my college computer architecture design project! Nowadays it must seem like a history book, since it concerns designing DEC-compatible minicomputers. But the thrill of design and hunting down and quashing elusive bugs is timeless.

Shine On You Crazy Designers

Denali is famous for throwing the best parties at DAC. I wish I had been there to see these performances. See more at YouTube - DenaliDacParty's Channel.

A Chip Carl Sagan Would Be Proud Of

Remember the great astronomer Carl Sagan? He had a famous catch phrase describing the enormity of the universe, talking about "billions and billions" of objects.

Well, the semiconductor world has our first giga-transitor chip as shown in AnandTech: NVIDIA's 1.4 Billion Transistor GPU: GT200 Arrives as the GeForce GTX 280 & 260. Check out the article's die shot, which compares the GT200 GPU next to an Intel Penryn CPU. What a tour de force! Imagine all the EDA tools that chip must have broken, leaving vendors quaking in their shoes. :-)

In reading up on Carl Sagan,

• I was reminded of the petty and very amusing feud between Sagan and Apple Computer.
• I learned that "the indefinite and fictitious number Sagan has arisen in popular culture to indicate a count greater than 4 billion." Thanks to Moore's Law, we'll see the first "Sagan-chip" before you know it.