Power Management DesignLine | Low Power CMOS Circuit Design is an excellent survey of CMOS power consumption along with the most common techniques to reduce power.
This article is a good quick reference -- why, these questions might even come up in an interview! ;-)
I wonder what tricks they're using for power-efficient design?
I've heard the IEEE-USA referring to such numbers, too. I think their interest is a combination of wanting to strengthen American competitiveness, but also to ensure increased funding for engineering education and research. In other words, self-serving for the greater good!
I wasn't sure to make of Cadence's announced Power Forward Initiative. This is such a nascent field, do we know what to standardize?
But then I could think of some design practices that would be very good to have a standard way to describe and verify, such as what voltage and power domains various parts of the design should be connected to, what is the design convention for isolation and level shifting, etc.
This could be a useful standard. Let's hope it doesn't degrade into another Cadence vs. Synopsys "we have two standards so we have no standard" like ECSM and CCS libraries!
