Development work is five times cheaper here

‘Development work is five times cheaper here’ is the claim by the CEO of ATI Technologies, commenting on their Hyderabad R&D center.

There are certainly very attractive aspects to setting up shop in India, but this article is a little over the top. I wonder if it's because this story is published for an Indian audience, or if it's because ATI has only been doing R&D there for a year, and perhaps hasn't seen the tradeoffs through a full product cycle?

The Power of the Xbox 360 GPU

The Power of the Xbox 360 GPU is a very informative interview with a VP of Engineering at ATI. He speaks in reasonable detail about what's in the custom graphics chip of the Xbox 360 game console. He contrasts it with conventional GPU architecture, and of course espouses why it must be better than what NVIDIA will provide in the Sony PlayStation 3 GPU.

The Xbox 360 GPU, "Xenos", is actually a two-chip implementation, and one of the chips has a big embedded DRAM! Although lots of ASIC vendors talk about doing this, you don't see it often in practice. Performance-wise, it makes sense, as you get huge memory bandwidth via the very wide interface to the DRAM.

SNUG: Synopsys Users Group - San Jose Conference at a Glance

SNUG is coming! The flagship San Jose Synopsys Users' Group meeting starts on March 20, 2006. Here is the conference schedule.

I've always felt this is the best conference for the "in the trenches" chip design engineer. It's very practical, with good tutorials, keynotes, and a healthy dose of user papers.

As I was signing up this year, I noticed that almost all the sessions I signed up for were Panels or Tutorials, not User Sessions. I wonder if the conference schedule is shifted away from user papers this year, or if my interests just happen to be with the other topics. It would be interesting to look at the split of types of sessions over the years. Well, not so interesting that I'm actually going to do the study, though. ;-)

Library standardization effort takes flight

Library standardization effort takes flight

There is a need for standardization of modeling for Statistical STA, though that whole technology is not well understood. It may be too early to standardize!

It would be great to settle the CCS vs. ECSM divide, however. These are essentially the same modeling approach, yet defined differently by Synopsys vs. Cadence/Magma, respectively.

I have sympathies for Si2 in trying to forge these standards across EDA companies. I was more involved in the days of Liberty, DCL/DCM, and ALF standardization, and it was very hard to get cooperation across all EDA vendors. They see Standards as an area to maneuver for competitive advantage.

Leakage takes priority at 65 nm

Leakage takes priority at 65 nm in EE Times is a nice survey of the experience of 65nm IC designs so far.

I noted that Statistical Timing Analysis was called a "must-have" technology, because of all the combinations of operating conditions when you have multiple voltage islands.

Two Win Prestigious Engineering Award - New York Times

Two Win Prestigious Engineering Award - New York Times

Cool! It's nice to see a couple of great engineers prominently recognized for their great contribution to technology (37 years after the invention of the CCD)!