Down with FinFETs, Up with Materials!

EETimes.com - FinFETs may never come in, IBM fellow claims

FinFETs (transistors where the channel gets pinched off from both sides) sound like pretty slick design solutions, and several companies and many universities are studying them. But this IBM researcher predicts that they aren't manufacturable. Instead, industry needs to focus on advanced materials for the traditional "planar" transistor technology.

Managing variations in IC physical design

EETimes.com - Managing variations in IC physical design is a great paper on the design closure challenges facing nanometer-scale IC design.

The author, Shankar Krishnamoorthy of Sierra Design Automation, describes the very typical timing analysis and design closure flow, where many different modes and PVT corners must be considered, yet closure tools only understand one or two of the scenarios.

The rigorous treatment of design variation, classified in a matrix of variablility "causes" vs. "effects", is the best treatment I've seen in a public article. (EDA vendors will show similar analyses when privately pitching their new variation-aware products.)

Surprisingly, the author does not conclude that "statistical" timing analysis, which is all the rage in the EDA community, is a panacea. He points out the difficulties of getting statistical characterization data for process, libraries, and interconnect. He also asserts that Hold time violations require analysis at whichever corner most aggravates a particular violation (calling for multi-corner analysis).

Very thought provoking! It will be interesting to see what products Sierra comes up with to address this growing IC design closure problem.

Teardowns find 'Microsoft Inside' Xbox 360

Here's another, more detailed, Xbox 360 "reverse engineering" article: EETimes.com - Teardowns find 'Microsoft Inside' Xbox 360.

Most of the chips have Microsoft's label on the package. At least in the case of the GPU, I believe that Microsoft bought the design from ATI and is paying royalties. I've read that this is a different business model from that of the original Xbox. Microsoft apparently wants more control over the silicon and any cost reduction efforts.

Microsoft's Red-Ink Game (Xbox 360)

Microsoft's Red-Ink Game provides cost estimates of the just-released and super-hyped Xbox 360 game console. Estimates are that it costs $126 more that the sale price to build the box.

Looking just at the chips, this machine has some expensive silicon:

Semiconductors alone account for $340, -- more than 72% of the materials cost -- iSuppli estimates. One key component, the IBM-designed microprocessor chip at the center of the console (see BW Online, 10/25/05, "Inside IBM's Xbox Chip") costs about $106. Both IBM and Chartered Semiconductor (CHRT) of Singapore are building the chip for Microsoft.

ROOM FOR IMPROVEMENT. Analyst Chris Crotty with iSuppli says that as both companies improve their manufacturing efficiency and production yields, they will likely reduce the chip's cost by 20% to 25%. The same will likely apply to ATI (ATYT), which is building the graphics-processing unit, or GPU, for the Xbox. iSuppli estimates that the chip is the most expensive component in the system at $141.

And how about the cost of the Sony PlayStation 3, to be released next year?

Crotty expects that Sony's loss on the Playstation 3 may be even wider, as the cell processor that IBM, Toshiba, and Sony designed for the system is more complex.

Estimates vary as to how much the cell processor will cost. Richard Doherty of Envisioneering Group in Seaford, N.Y., expects the cell chip to cost about 50% more than the Microsoft chip. "Based on what we've seen so far, the Playstation 3 could cost as much as $600 to make in today's pricing," Doherty says.

And Crotty says that since it's a more complex chip, its price will fall more slowly than the price on the Xbox chip.

Ouch! No wonder the games cost $60 per title, to make up for the hardware losses.

Sramana Mitra on Strategy

I enjoy this blog by Sramana Mitra, who is a technology and business prognosticator. His Her blog both covers the big picture and contains nuggets of individual business/career opportunities, such as

Configuring and managing Home Networks will be a big profession, and this job cannot be outsourced as easily. A largely non-tech savvy consumer population will demand that service personnel come out to their homes and fix things. Who pays? Consumer or Carrier? Without this support, Convergence will not cross the chasm.

-- Sramana Mitra on Strategy; Blog Archive; Cisco: Inching Us to True Convergence

11/22 UPDATE: A loyal reader (from India) pointed out that Sramana is a woman, not a man. My apologies! I've corrected my wording.

ICCAD keynote | Gabe on EDA

Tets Maniwa's article (on the Gabe on EDA blog) summarizing the ICCAD keynote is a well-written overview of the Cell processor design tradeoffs.

I'm sorry I missed ICCAD; it's right here in Silicon Valley. I need to get on the right mailing list to hear about such things. It's not as practical a conference as SNUG, but it's a good resource for a look at future design technology.

EETimes.com - Alarming export: engineers

For a long time (since even I was a college student), US Engineering graduate schools have been populated primarily by foreign-born students, particularly from China, Taiwan, and India.

It used to be that such student would typically stay in the US to work. This was controversial, requiring H1B visa, and some allegations of taking American jobs or depressing wages.

Today, these students aren't necessarily sticking around. They're going back to work in their home countries, where they may be more comfortable or sense more opportunity. An example of this is described in EETimes.com - Alarming export: engineers.

Now these very bright students are taking their knowledge and work ethic back home. It's probably a net loss to the US to not have them sticking around. It shows you should be careful what you wish for!

Semiconductor Workforce Demands and Opportunities

Semiconductor Workforce Demands and Opportunities lists the specific job titles that semiconductor employers are looking for hardest.

It's an interesting list. Some of it makes sense, some doesn't. It would be best for me to look into the Analog/Mixed-Signal (AMS) field, since I'm not qualified to fill the African-American or Female Technicals openings.

Magma plans tools to address complexity challenges

Magma plans tools to address complexity challenges is an intriguing pre-announcement. What will this "thing" be?

There's always tension between wanting a "one-stop-shop" with a highly integrated environment and flow, and wanting "best of breed" tools that produce the best, fastest results. Best of breed usually wins. Getting to an integrated environment? That's what CAD departments are for. ;-)

John Cooley's DVcon'05 Trip Report

DVcon'05 Trip Report:
-or-
A Census of 338 Engineers on Design Verification Tool Use

is chock-full of EDA data painstakingly compiled by John Cooley.

It's nicely organized, and the summary at the top of each subject is well worth a read. As you get further into each article, there are a lot of one-line responses that aren't very informative, though you can get a feel for what other companies are doing.

Intel's Ultra Low-Power Process

There was a story a couple of days ago about Intel announcing an ultra-low power 65nm process. I've been looking around and couldn't find much technical detail, but New Intel 65 nm lithography promises reduced leakage for small devices at Tom's Hardware Guide has the most detail.

The power reduction is through a three-pronged attack:

1. Increasing treshold voltage. This is familiar to all nanometer-scale digital IC designers today.
2. Low Damage Junction Engineering. Uh, that's some real process engineering, and I don't have much insight.
3. Increased Gate Oxide Thickness. This is very interesting and counter to scaling and performance trends. But, when the gate oxide is only 3-5 atoms thick, you have to question "how thin is too thin?". The article just mentions making the oxide thicker. Presumably this is less risky than utilizing often-mentioned but not-in-production High-K Dielectrics.

Startup claims FPGA lead with asynchronous logic

EETimes.com - Startup claims FPGA lead with asynchronous logic one of a handful of claims for products based upon asynchronous logic design.

I'm very intrigued by this idea. It has the promise of removing lots of overhead in chips for clock distribution and balancing. Not only does all the synchronous clock overhead use a significant amity of chip area, but it uses up a large amount of the standard cell power consumption! Every one of those clock buffers toggles twice per period, giving it a "toggle factor" of 2X.

I don't recall asynchronous logic design being taught in any of my engineering classes. There need to be more resources to learn about it.

Another big roadblock is that there is not the EDA infrastructure for asynchronous design. All the commercial synthesis, timing, and test tools assume synchronous design.

Designing ICs with the 'X' Architecture

EETimes.com - Designing ICs with the 'X' Architecture is a great exposition of the emerging design style of using diagonal interconnect in addition to the traditional Manhattan (horizontal and vertical only) routing.

The good news about EDA

It is good to recognize the exciting things that our industry is accomplishing, as described in EETimes.com - The good news about EDA by Richard Goering.

I agree that SystemVerilog looks to be a better way to design and verify. It's more productive, removes some Verilog ambiguity, and has better support for formal verification.

I don't know the prospects for OpenAccess (hope it's not another CAD Framework Initiative or CHDSTD), but hope it succeeds. As Richard says, why should every startup (and every corporate CAD department) have to redevelop the infrastructure for EDA tools?

Don't know much about SystemC. Let's start using SystemVerilog first.

Intel Developer Forum August 2005 coverage

The Intel Development Forum got tons of press. Intel is running away from the "most gigahertz" school of CPU design because of the stifling problems of power management. I'll link the best articles with IDF coverage here:

• Intel Developer Forum August 2005 full coverage
• Intel abandons GHz war, embraces cool future | The Register

NVIDIA scientist calls for expanded research into parallelism

Update: this article in BYTE magazine (subscription required) describes how Intel really wants programmers to write parallel code.

This EE Times report from the Hot Chips conference, NVIDIA scientist calls for expanded research into parallelism, raises one of the "dirty little secrets" of all the hype about multi-core CPUs -- it is hard to make applications multi-threaded! Do we already have a good programming language for describing an application's parallelism, or is a new language needed?

Meanwhile, those working in the graphics arena are ideally suited to taking advantage of Moore's Law:

Kirk contrasted this situation against the entirely different structure inside the GPU. "Graphics has been called embarrassingly parallel," he said. "In effect, each stage in our pipeline, each vertex in the scene and each pixel in the image is independent. And we have put a lot of effort into not concealing this parallelism with programming."

This allows a GPU developer to simply add more vertex processors and shading engines to handle more vertices and more pixels in parallel, as process technology allows. "We are limited by chip area, not by parallelism," Kirk observed.

Xbox 360 Die Photos

Ever wonder what's in the chips that power the most powerful game consoles? Well, Xbox 360: New Tech Specs Details Surface - Xbox has die photos of both the CPU and GPU for you to oogle.

Each of these contains more transistors than an AMD Atlon64 CPU. There is a lot of power (both computing and electrical) in these chips!

EDA pioneer takes startup to new routing ground

EDA pioneer takes startup to new routing ground is a nice glimpse of this history of John Cooper, an old-time EDA guru, and looks to the future at a new type of router that his startup is developing.

I like the article more for this history than any insight I have into their new router's prospects. Also very impressive is the amount of money that Cadence paid to acquire CCT. It would be really interesting to do an analysis of what EDA vendors have paid for acquisition, and what returns they got. How about Cadence's acquisitions of Ambit and HLD Systems? HLD in particular didn't see to last long.

The Dangers of Living with an X (Bugs Hidden in your Verilog)

The Dangers of Living with an X (Bugs Hidden in your Verilog) is a technical paper that is important for ASIC design and verification engineers. It's an exhaustive analysis of interpretation of the 'X' value in Verilog HDL. This detail is often misunderstood and can be dangerous in design. The paper was originally presented at SNUG. It says the author won the Technical Committee award. I'm surprised he didn't win additional awards -- it's one of the best ASIC design papers I've read.

Constructing the next transistor

Constructing the next transistor , in EE Times, is a superb article describing the technical challenges to building useful transistors below 65nm. It covers the physical and materials challenges that are arising, and how the solution to one problem (e.g., low leakage power) may aggravate another (high performance).

I'd love to have seen this illustrated with some pictures -- I wonder if the print edition has that? In any case, if you're a semiconductor engineer or scientist, you'll find this article worthwhile.

Why, it even makes me want to dust off my semiconductor textbooks to remember what's really going on inside a MOS transistor!

EDA Vendor Earnings Announcements

I admit I'm not a financial guru, but trounces seems like a strong word for "Cadence recognized net income of just $500,000, or $0.00 per share"!

UPDATE: Synopsys will announce their 3Q2005 earnings on August 17.

• Cadence Trounces Guidance Again
• Magma Reports Fiscal Q1 Sales Up 8% The fourth largest EDA tool supplier reported record high revenue of nearly $39 million for the fiscal quarter ended July 3.
• Mentor Q2 Sales, Earnings Fall Due to lower than expected bookings, the third largest EDA player saw both revenue and earnings per share fall, but remains positive for future growth for new and emerging products.

CDNLive! Conference

Cadence's answer to SNUG, the Synopsys User Group, is CDNLive! The schedule looks pretty good -- interesting and relevant. Looks like they also managed to get customers to present their advanced product experiences rather than relying on their own marketing pitches. If you're interested, early registration discount ends on August 12.

Improving yield in RTL-to-GDSII flows

I'm very curious about how front-end or RTL design can influence manufacturability or yield in a Standard Cell flow. I don't see the connection.

Improving yield in RTL-to-GDSII flows sounds like it would explain it all for me, but the connection to RTL design still seems to be missing. I see where synthesis might be able to select cells out of a "high yield" library (if such a beast existed), and certainly there are things to do during routing, such as adding redundant vias. But this is all physical design. Is the logic designer off the hook?

A Plethora of White Papers

Magma Design Automation, Inc. - White Papers lists a number of relevant and well-written White Papers, including non Magma-specific topics such as

• Signal Integrity
• Visualizing the behavior of Logic Synthesis algorithms

Some of the other papers are more oriented to Magma tool capabilities, but because their tool suite is modern and novel, they should be informative as well.

Designing for New Dimensions

This is very "researchy" stuff, but it could dramatically reduce interconnect length, much better even than "X Architecture". Designing for New Dimensions refers to the third dimension, previously unexploited in IC design. And a picture is worth 10^3 words:

Retrospective on DAC and EDA

Ditchin' DAC is a long-time DAC veteran's take on the evolution of the Design Automation Conference, from the beginnings as a clearinghouse of Corporate CAD developments, through the booming tradeshow of the 1990s, to now, where some question whether DAC is worth the cost and time. I'm on the fence. I'd go to DAC if it were local, but usually can't justify the time and expense to travel there. DAC hasn't been in the Bay Area in several years, although we probably have the greatest number of industry customers.

Tenzing Norgay Interoperability Achievement Award?

This has long struck me as the most incongruous award in our industry: ARM Recipient of Synopsys Fifth Annual Tenzing Norgay Interoperability Achievement Award. Yes, I know who Tenzing Norgay is, but the connection to EDA??? It reminds me so much of Apple using pictures of Einstein and Gandhi to promote their products.

Interoperability plays a key role in elevating designers to a higher level of productivity, just as Tenzing Norgay's efforts facilitated the first ascent to the top of Mount Everest, said Rich Goldman, vice president, Strategic Alliance at Synopsys.

Ah, it all makes sense now. ;-)

Hot Chips' Conference Preview

EETimes.com - Hot Chips' message: It's the bandwidth gives a head-up as to the themes to be presented at the August Hot Chips conference. The top problems designers face are

1. Managing power
2. Managing the memory bandwidth bottleneck

Here for the foreseeable future is a world of parallelism, of increasingly application-directed architectures and of an unending struggle for memory bandwidth rather than Mips.

The RISC that did not pay off

EETimes.com - The RISC that did not pay off points out that while Reduced Instruction Set Computing was the rage starting in the 1980s, the reasons for its appeal are no longer dominant. Memory bandwidth has become a huge bottleneck, which wasn't the case when RISC was on the ascent.

LSI Logic RapidChip & Structured ASIC

I've always been intrigued by initiatives to bring down the ever-increasing cost of nanometer-scale IC design. While mask sets can cost more than $1M, I fondly remember the days of Gate Array vendors' ability to turn prootypes in less than a week! LSI Logic's Leverage reads like a PR piece written by LSI Logic about RapidChip, their Structured ASIC product. While intrigued, I want to understand about these technologies:

1. How do they know what IP to diffuse onto the base layers? How do you reconcile if one customer wants N Serdes macros, and another wants M megabits of RAM?
2. Who is really using Structured ASIC? How real is it, and for what applications?

Sequence CoolPower: SoC Power and Voltage Drop Optimization

Sequence CoolPower First with Comprehensive SoC Power and Voltage Drop Optimization; New Automated MTCMOS Power Gating Slashes Leakage up to 100X, CoolPower Reduces Voltage Drop Significantly with No Timing/SI Penalty is in the running for the longest-titled Press Release! The march toward low-power methodologies continues. While Vth optimization is localized and has few side effects, emerging techniques such as Power Gating have implications for design, verification, and implementation methdologies. I don't know how cleanly this works yet. Sequence is announcing a product to support this, and I imagine the big EDA players will address this as well. BTW, Sequence neglected to define MTCMOS. It stands for Multi-Threshold CMOS. The idea is that the regular functional transistors are low-threshold (high-speed, high leakage), but the power to these transistors is gated by a high-threshold transistor during non-operation or "sleep".

Discovering Multi-Core: Extending the Benefits of Moore's Law is a well-written laymen's description of the challenges to Moore's Law as we face physical limits in scaling chips.

• The argument for "scaling out" is similar to NVIDIA's SLI strategy, which links two GPUs to work in parallel on graphics rendering.

Reflections on DAC

Reflections on DAC by Gabe Moretti is an good overview of this year's Design Automation Conference. Other than his tedious attempt to define a new taxonomy for the EDA market, I enjoyed his observations about the show and analysis of the big EDA vendors.

Sony May Lose Up to $1.18 Billion on PlayStation 3 – Merrill Lynch

Sony May Lose Up to $1.18 Billion on PlayStation 3 – Merrill Lynch is an interesting analysis of the economics of game console hardware. ... estimates that the machine’s main components – namely its Cell chip, NVIDIA RSX graphics processor and BD-ROM drive – will cost about $101 each. Oh well, they will sell a lot of $50 game CDs to recoup the hardware cost!

Do we have a brain balance deficit?

EDA analyst Gabe Moretti has written an insightful analysis of offshoring and issues facing engineers in particular. Take a gander at Do we have a brain balance deficit?. I agree that H-1B workers are better for the US than offshore outsourcing! I also relate to his observations on why an engineering career isn't as attractive as medicine or law.

Delay of ATI R520 to boost Nvidia 4Q sales

An interesting explanation inDelay of ATI R520 to boost Nvidia 4Q sales: the company is facing leakage issues, as it attempts to migrates its manufacturing to a 90nm process It is rare to see such a specific attribution of production problems! I wonder what techniques they are using and what's not working? Vth optimization? Power Gating? ...

EDA startups tout more nimble physical design

Startups at DAC fielding interesting new products were covered in EETimes.com - Three tout more nimble physical design

• Magma's Quart-DRC high-performance distributed DRC.
• Apache PsiWinder critical-path and clock tree analysis tool that considers crosstalk and dynamic-power integrity effects.
• Sierra Pinnacle physical-synthesis tool to concurrently optimize timing, area, power and signal integrity across all operating modes and corners.

Xbox 360 unlikely to outsell PS3

This story describes a detailed market analysis for next-generation game consoles. It's very hard to predict how things will play out, but from the sound of it, I'm glad that Sony and NVIDIA are together for the PS3.

ATI, Cadence and TSMC Produce X Architecture Chip

The X Architecture initiative, an early example of which is described in ATI, Cadence and TSMC Produce Industry's First Fabless X Architecture Chip, is based on a straightforward idea: rather than run all the wires on an IC horizontally and vertically (Manhattan routing), devote a couple of layers to routing diagonally at 45 and 135 degrees. It allows you to "cut the corner" and routing distances become shorter. I think the biggest challenges to making this work are on the manufacturing side, which is why there's been heavy involvement from foundries like TSMC and semiconductor equipment manufacturers. I first heard about the X Initiative when Simplex Solutions and Toshiba were working on it several years ago. Cadence acquired Simplex, and this technology is starting to be introduced commercially now. UPDATE: This article has more technical detail.

TSMC Reference Flow 6.0

TSMC issued a press release to announce their Reference Flow 6.0. It emphasizes (1) low-power design, including building blocks for a "power gating" methodology, and (2) Design For Manufacturing. It's also interesting that TSMC's trend is to integrate more value-add rather than be a 100% pure manufacturer. For example, TSMC is offering their own libraries for standard cells, memories, and I/O. It may be that this is natural, given the increasing relationship between Design and Manufacturing. But it should also help their business margins as they add more value. UPDATE: EETimes.com - TSMC reference flow heralds 65-nm transition

ChipEstimate.com

ChipEstimate.com is a very interesting concept to help a chip management team "size up" a proposed IC. Based on high-level information about gate count and IP used, it comes up with a floorplan and, at an additional cost, will provide budget estimates for manufacturing the chip with various foundries' processes. I remember that eSilicon had a similar budgeter, though it was intended for designs to be done with eSilicon. This ChipEstimate.com appears to be a standalone estimation product.

Design for Manufacturing: What Designers Need to Know About the Change in Yield Management

I've been reading this paper, Design for Manufacturing: What Designers Need to Know About the Change in Yield Management, at lunchtime, and find it to be an excellent overview of all the "DFM" effects that you hear about. Antenna effects, need for metal fill, what's wrong with Copper, are all topics that are covered in an introductory way. Nice starter!

IBM markets statistical timing analyzer

EETimes.com - IBM markets statistical timing analyzer announces IBM's (re-)entry into the commercial EDA market. "Statistical STA" is new and hot. It should allow for less pessimistic STA, which becomes a critical requirement around 65nm. If you guardband to assume that every parameter is 3-sigma worst case, that's an unrealistic situation. A Statistical STA tool would understand that what combination of variations would happen with 3-sigma probability. Magma plans to launch a tool, but I haven't seen Synopsys or Cadence announce anything. Another type of variation is "location-based correlation". I don't see that addressed by the IBM STA tool.

Xbox 360 GPU Details

Xbox 360 GPU Details goes into some detail about ATI's GPU for the next Microsoft console. What's particularly interesting and impressive are the efficiency claims and the use of embedded DRAM.

E3: Game Console Wars and Booth Babes

E3: Game Console Wars and Booth Babes provides a very good overview and comparison of the next-generation gaming consoles. As for the ultimate winner, it's way to early to know. But the article does take Sony to task for showing too much "smoke and mirrors", whereas Microsoft is showing real development. You have to read all the way to the end to see the "Booth Babes", but they are in there! Nothing like any conference I've ever been sent to!

Line blurs between graphics IC and CPU

I've been wondering about the role of the NVIDIA GPU vs. the Cell processor in Sony's Playstation 3, and this article explores some of the tradeoff possibilities. Both chips can do high-powered vector processing. Apparently the Xbox 360 and ATI GPU have similar opportunities for sharing the workload. The ATI multi-die packaging is unique. (Is that good or bad?)

SYNTHESIS:'Topological' tool improves postlayout timing, area

This could be a welcome breakthrough by Synopsys Design Compiler: 'Topological' tool improves postlayout timing, area. Also, see the Synopsys Press Release. It isn't new to include placement with synthesis (that's what Physical Synthesis is), but if they include this in DC-Ultra logic synthesis, it's easy to use, and it correlates to Layout, then that's a big win.

Console Wars! Playstation 3 doubles Xbox 360 performance

It's going to be interesting watching the next generation of game consoles come out next year. All three vendors provided previews of their systems in the last week, see EETimes.com - Playstation 3 doubles Xbox 360 performance. It's exciting the NVIDIA is partnered with such a successful leader in Sony. There is some description of the NVIDIA "RSX" graphics chip in the article. Onward! Update: PlayStation 3 stats spotlighted

Silicon Design Systems Delivers Next-Generation Router

Silicon Design Systems Delivers Next-Generation Router. Well, it is a press release, but it certainly sounds like a novel routing approach. Would be interesting to learn more. Also novel is the company's heritage: originally a design services firm, they've now decided to develop EDA tools. Although EDA can be a small market, there's potential for higher margins (and possible acquisition) that company's can't enjoy as a "services" firm.

Atrenta RTL Analysis Products

I've become interested in RTL checking (linting) tools, and Atrenta has one of the most comprehensive offerings. They have introduced a new set of products (some repackaged from SpyGlass) and the new product family is called "1Team". 1Team:Analyze 1Team:Verify SpyGlass� Constraints Demonstration Update: In addition to the above company press releases, here's an overview by Richard Goering @ EE Times. EETimes.com - VERIFICATION: Atrenta adds analysis to suite of 'predictive' tools

Toshiba Demonstrates Cell Microprocessor Simultaneously Decoding 48 MPEG-2 Streams

On of the most-hyped chips on the horizon is the Sony/Toshiba/IBM Cell Microprocessor. Will it render today's microprocessors and graphic chips obsolete? It is slated to go into Sony's Playstation 3 (along with an NVIDIA GPU) and also many other consumer electronics applications. An early demonstration of the chip is reported in Toshiba Demonstrates Cell Microprocessor Simultaneously Decoding 48 MPEG-2 Streams -- Tech-On!. Especially interesting is the interview linked at the bottom with Sony's "Father of the Cell Chip".

IBM's Strained Silicon

I Googled around and this is one of the authoritative descriptions of strained silicon: IBM's Strained Silicon Page. I'd like to find more info on how new processes such as this and silicon-on-insulator (SOI) affect the requirements for EDA tools and flows.

TSMC sees low-power process as new technology driver

EETimes.com - TSMC sees low-power process as new technology driver is a nice summary of this week's TSMC Technology Symposium, which I attended for the first time. The symposium and exhibitors were very informative. Need to read up on strained silicon!