tag:blogger.com,1999:blog-12511368.post113945011206250203..comments2024-01-13T14:13:13.679-08:00Comments on John's Semi-Blog: Digital designer's plight debated at ISSCCJohnhttp://www.blogger.com/profile/08635360760744356704noreply@blogger.comBlogger2125tag:blogger.com,1999:blog-12511368.post-1139536986857138322006-02-09T18:03:00.000-08:002006-02-09T18:03:00.000-08:00Thanks Sandeep. With respect to "working at system...Thanks Sandeep. With respect to "working at system level", do you read the<BR/><A HREF="http://chipsandbs.blogspot.com/" REL="nofollow">Chips and BS</A> blog?<BR/>It covers ESL.<BR/>The author is an "informed partisan", from one of the ESL design companies.Johnhttps://www.blogger.com/profile/08635360760744356704noreply@blogger.comtag:blogger.com,1999:blog-12511368.post-1139460521815927722006-02-08T20:48:00.000-08:002006-02-08T20:48:00.000-08:00I think as chip designs are pushed beyond 65 nm, t...I think as chip designs are pushed beyond 65 nm, the lines between digital and analog logic will keep on blurring.<BR/>Think of synthesis tools that know that generating a ripple-adder in a particular case will cause too much leakage.<BR/><BR/>However, I (and the rest of my comrades!) are betting that working at system level will be where today's digital designers will work tomorrowSandeephttps://www.blogger.com/profile/08059484663197335523noreply@blogger.com